stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 33

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

III - FUNCTIONAL DESCRIPTION (continued)
III.5.5.2 - 1M x n DRAM Signals
The Address bits delivered by the Multi-HDLC for
1M x n DRAM circuits are :
ADM0/9 (2 x 10 = 18 bits) correspondingwith A1/20
delivered by the P.
Figure 21 : 1M x 16 DRAM Circuit Organization
III.5.5.3 - 4M x n DRAM Signals
The Address bits delivered by the Multi-HDLC for
4M x n DRAM circuits are :
ADM0/10 (2 x 11 = 22 bits) corresponding with
A1/22 delivered by the P.
NRAS3
NRAS2
NRAS1
NRAS0
ADM0/9, NWE, NOE a re connected to each circuit
Signals
NRAS3
NRAS2
NRAS1
NRAS0
NCAS1
NCAS0
Signals
NRAS1
NRAS0
NCAS1
NCAS0
NCAS1
7
5
3
1
A22
1
1
0
0
DM8/15
A23
1
0
A20
NCAS0
1
0
1
0
6
4
2
0
DM0/7
A0 or equiv.
A0 or equiv.
1M x 16
1
0
1
0
Figure 22 : 4M x 16 DRAM Circuit Organization
III.6 - Bus Arbitration
The Bus arbitration function arbitrates the access
to the bus between different entities of the circuit.
Those entities which can call for the bus are the
following :
- The receive DMA controller,
- The microprocessor,
- The transmit DMA controller,
- The Interrupt controller,
- The memory interface for refreshing the DRAM.
This list gives the memory access priorities per
default.
If the treatment of more than 32 HDLC channels is
required by the application, it is possible to chain
several Multi-HDLC components.That is done with
two external pins (TRI, TRO) and a token ring
system.
The TRI, TRO signals are managed by the bus
arbitration function too. When a chip has finished
its tasks, it sends a pulse of 30 ns to the next chip.
Figure 23 : Chain of n Multi-HDLC Components
NRAS1
NRAS0
ADM0/10, NWE, NOE a re conne cte d to e a ch circuit
P
P Bus
NCAS 1
3
1
DM8/15
MHDLC 0
MHDLC 1
MHDLC n
TRO
TRO
TRO
TRI
TRI
TRI
NCAS 0
2
0
DM0/7
RAM Bus
STLC5464
4M x 16
RAM
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