adc0808s125 NXP Semiconductors, adc0808s125 Datasheet - Page 5
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adc0808s125
Manufacturer Part Number
adc0808s125
Description
Single 8-bit Adc, Up To 125 Mhz Or 250 Mhz
Manufacturer
NXP Semiconductors
Datasheet
1.ADC0808S125.pdf
(23 pages)
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7. Functional description
ADC0808S125_ADC0808S250_2
Product data sheet
7.1 CMOS/LVDS clock input
Table 3.
The circuit has two clock inputs CLK+ and CLK , with two modes of operation:
Type
I
O
I(CMOS)
O(CMOS)
P
G
Fig 3. LVDS clock input
Fig 4. CMOS clock input
•
•
LVDS mode: CLK+ and CLK inputs are at differential LVDS levels. An external
resistor of between 80
1.8 V CMOS mode: CLK+ input is at 1.8 V CMOS level and sampling is done on the
rising edge of the clock input signal. In this case pin CLK must be grounded;
see
Figure
Pin type description
4.
V
Description
input
output
1.8 V CMOS level input
1.8 V CMOS level output
power supply
ground
O(dif)
DRIVER
Rev. 02 — 7 October 2008
LVDS
and 120
DRIVER
CMOS
V
gpd
is required; see
Single 8-bit ADC, up to 125 MHz or 250 MHz
CLK+
CLK
RECEIVER
undefined state
001aai272
ADC0808S125/250
CLK+
CLK
Figure
maximum V
minimum V
3.
001aah720
idth
idth
© NXP B.V. 2008. All rights reserved.
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