adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 21

• Manufacturer Part Number: adc1213d125hn/c1
• Description: Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
Fig 21. General overview of the JESD204A serializer
S samples per frame cycle
N bits from Cr
CS bits for control
SYNC~
CS bits for control
N bits from Cr
M CONVERTERS
N' = N+CS
M−1
0
14.5.1 Digital JESD204A formatter
+
+
14.5 JESD204A serializer
Mx(N'xS) bits
lane stream mapping
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
samples stream to
TX transport layer
Fig 20. CML output connection to the receiver in AC coupling
CF: position of controls bits
Padding with Tails bits (TT)
HD: frame boundary break
All information provided in this document is subject to legal disclaimers.
L LANES
F octets
F octets
+
Lx(F) octets
Rev. 05 — 23 April 2010
OCTETS
OCTETS
FRAME
FRAME
VDDD
TO
TO
12 mA to 26 mA
L octets
50 Ω
−
SCRAMBLER
SCRAMBLER
CMLPA/CMLPB
CMLNA/CMLNB
10 nF
10 nF
TX CONTROLLER
CHARACTER
GENERATOR
CHARACTER
GENERATOR
ALIGNMENT
ALIGNMENT
ADC1213D series
100 Ω
10-bit
10-bit
8-bit/
8-bit/
RECEIVER
005aaa083
ADC1213D series
© NXP B.V. 2010. All rights reserved.
005aaa084
SER
SER
LANE0
LANE1
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