adc1213s125hn/c1 NXP Semiconductors, adc1213s125hn/c1 Datasheet - Page 33
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adc1213s125hn/c1
Manufacturer Part Number
adc1213s125hn/c1
Description
Adc1213s Series Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Serial Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1213S125HNC1.pdf
(39 pages)
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NXP Semiconductors
Table 45.
Default values are highlighted.
Table 46.
Default values are highlighted.
ADC1213S_SER
Product data sheet
Bit
2
1
0
Bit
7 to 6
5 to 4
3 to 1
0
Symbol
LANE_POL
RESERVED
LANE_PD
Symbol
-
ADC_MODE[1:0]
-
ADC_PD
Lane_0_Ctrl (address 0871h)
ADC_0_Ctrl (address 0891h)
R/W
R/W
-
R/W
Access
R/W
Access
R/W
-
All information provided in this document is subject to legal disclaimers.
…continued
Value
0
1
0
0
1
Value
00
00 (reset)
01
10
11
000
0
1
Rev. 1 — 14 March 2011
Description
defines lane polarity:
reserved
lane power-down control:
Description
not used
defines input type of JESD204A unit
not used
ADC power-down control:
lane polarity is normal
lane polarity is inverted
lane is operational
lane is in Power-down mode
ADC output is connected to the JESD204A input
not used
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
ADC is operational
ADC is in Power-down mode
Single 12-bit ADC; serial JESD204A interface
ADC1213S series
© NXP B.V. 2011. All rights reserved.
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