adc1004s030 NXP Semiconductors, adc1004s030 Datasheet - Page 9

• Manufacturer Part Number: adc1004s030
• Description: Single 10 Bits Adc, Up To 30 Mhz, 40 Mhz Or 50 Mhz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
V
V
V
[1]
[2]
[3]
[4]
[5]
[6]
ADC1004S030_040_050_3
Product data sheet
Symbol
Differential phase
Timing (f
t
t
t
C
3-state output delay times; see
t
t
t
t
d(s)
h(o)
d(o)
dZH
dZL
dHZ
dLZ
CCA
CCO
CCA
dif
L
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns.
Analog input voltages producing code 0 up to and including code 1023:
a) V
b) V
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter
reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors
R
a) The current flowing into the resistor ladder is
b) Since R
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
E
= V3 to V4 = 4.75 V to 5.25 V; V
= V
= V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T
OB
G
(V
to code 1023 at T
to 1023 is
will be kept reasonably constant from device to device. Consequently, the variation of the output codes at a given input voltage
depends mainly on the difference V
connected in parallel and fed with the same reference source, the matching between each of them is optimized.
and R
=
offset
offset
CCD
RB
clk
-------------------------------------------------------- -
) at T
Parameter
differential phase
sampling delay time
output hold time
output delay time
load capacitance
float to active HIGH delay
time
time
active HIGH to float delay
time
active LOW to float delay
time
Characteristics
V
float to active LOW delay
= 40 MHz; C
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
TOP is the difference between the reference voltage on pin RT (V
= 5 V and V
1023
OT
L
, R
amb
as shown in
V
–
OB
V
[9]
I
V
= 25 C.
i p
=
and R
0
–
R
amb
–
p
L
V
CCO
L
OT
= 25 C
i p
= 15 pF); see
Figure
I
have similar behavior with respect to process and temperature variation, the ratio
L
…continued
–
= 3.3 V; C
=
p
.
--------------------------------------- -
R
3.
Figure 5
OB
100
CCD
+
RT
L
R
R
L
L
= 15 pF and T
Conditions
f
PAL-modulated ramp
V
V
Figure 4
= V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
clk
+
CCO
CCO
V
RB
= 40 MHz;
R
OT
= 4.75 V
= 3.15 V
and its variation with temperature and supply voltage. When several ADCs are
I
=
Rev. 03 — 7 August 2008
[10]
V
--------------------------------------- -
R
RT
OB
V
amb
+
RT
+
V
R
= 25 C; unless otherwise specified.
–
RB
L
V
+
Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
RB
R
=
OT
0.852
and the full-scale input range at the converter, to cover code 0
Min
-
-
4
-
-
-
-
-
-
-
RT
ADC1004S030/040/050
) and the analog input which produces data outputs equal
V
amb
RT
= 0 C to +70 C; typical values measured at
–
V
RB
Typ
0.4
3
-
10
12
-
5.5
12
19
12
Max
-
-
-
13
15
15
8.5
15
24
15
--------------------------------------- -
R
OB
© NXP B.V. 2008. All rights reserved.
+
R
R
Unit
deg
ns
ns
ns
ns
pF
ns
ns
ns
ns
L
L
+
R
OT
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