adc1020 austriamicrosystems, adc1020 Datasheet

no-image

adc1020

Manufacturer Part Number
adc1020
Description
Cmos 10-bit Pipelined A/d Converter
Manufacturer
austriamicrosystems
Datasheet
ANALOG IP BLOCK
ADC1020 - CMOS 10-Bit Pipelined A/D CONVERTER
PROCESS
C35B3 (0.35um)
Revision C, 07.09.02
FEATURES
!
!
!
!
!
!
!
!
!
!
!
Small Area: 1.57mm
Size x= 2189.7µm y= 717.4µm
Supply Voltage 2.7-3.6 V
Junction Temp. Range −40 to +85°C
Resolution 10-Bit
Maximum Sampling Rate 20 MS/s
Sample and Hold Input Stage
2 Vpp or 4 Vpp Input Signal Range
Single Ended or Fully Differential Input
Power Consumption of 200 mW
Power Down Mode
ONREF
VBG
VCMU
ONCM
DOUT
VINP
VINN
CLK
SWIB
ONADC
DGT
2
REF
GEN
B
S/H
Bias Current Generation
VDDA1
VSSA1
Pipeline
ADC
Timing Generation
VSSAD
VDDA2
DESCRIPTION
The AD1020 is a high-speed pipeline ADC core cell
achieving sampling rates up to 20 MS/s. A S/H circuit is
built-in to provide low jitter noise and an optional single-
ended to fully differential conversion. The reference
voltages are internally generated from a bandgap
reference that must be supplied to the cell or must be
supplied externally to the cell. A power down capability
is included for very low power dissipation in stand-by
mode.
Correction
Digital
Error
VSSD1
VDDD1
Register
Output
VREFP
VREFN
IBIAS
VCM
B9
B0
Page 1 of 11
DATA SHEET

Related parts for adc1020

adc1020 Summary of contents

Page 1

... ANALOG IP BLOCK ADC1020 - CMOS 10-Bit Pipelined A/D CONVERTER PROCESS C35B3 (0.35um) FEATURES ! 2 Small Area: 1.57mm ! Size x= 2189.7µm y= 717.4µm ! Supply Voltage 2.7-3.6 V Junction Temp. Range −40 to +85° Resolution 10-Bit ! Maximum Sampling Rate 20 MS/s ! Sample and Hold Input Stage ! 2 Vpp or 4 Vpp Input Signal Range ...

Page 2

... Datasheet : ADC1020 – C35 TECHNICAL DATA (Tjunction=-40 to 85°C, VDDA=VDD=+2.7V to +3.6V, fclk=20MHz, VREFP and VREFN as specified, unless otherwise specified) DC ACCURACY Symbol Parameter Resolution (No missing Code) DNL Differential Linearity Error INL Integral Linearity Error OFF Offset Error 1) GAINERR Gain Error for Internal Ref. ...

Page 3

... Datasheet : ADC1020 – C35 AC ACCURACY (VREF=1V) Symbol Parameter THD Total Harmonic Distortion THD Total Harmonic Distortion THD Total Harmonic Distortion SFDR Spurious Free Dynamic Range SFDR Spurious Free Dynamic Range SFDR Spurious Free Dynamic Range SNR Signal to Noise Ratio SNR Signal to Noise Ratio ...

Page 4

... Datasheet : ADC1020 – C35 DIGITAL INPUTS AND OUTPUTS Symbol Parameter VDD Pos. digital Supply Voltage VSS Neg. digital Supply Voltage VIL Digital Input Level VIH VOL Digital Output Level VOH B[9:0] Output Code POWER REQUIREMENTS Symbol Parameter VDDA Pos. analog Supply Voltage VSSA Neg ...

Page 5

... Datasheet : ADC1020 – C35 TYPICAL PERFORMANCE CHARACTERISTICS (T=25deg, VDDA=VDD=+3.3V, fclk=20MHz, VREFP=2V, VREFN=1V, Op. Mode 1 and Fully Differential Mode, unless otherwise specified) DNL @180kHz Input Signal Frequency [Hz] Spectrum @180kHz Input Signal Frequency [Hz] Two-Tone IMD @4.0MHz and 4.5MHz 1) The spectrum consists of 16384 pins. 2) Measured with a 12MHz low pass filter for all frequencies. ...

Page 6

... Datasheet : ADC1020 – C35 SYMBOL THEORY OF OPERATION The AD1020 is a 10-bit ADC capable of sampling at 20 MS/s. It uses a fully differential pipelined architecture with 1.5-bit per stage and digital error correction to achieve improved linearity performance. A dedicated wide-band input sample-and-hold amplifier (S/H) is built-in to provide low-jitter, sub-sampling capability with inherent frequency down-conversion and, optionally, Revision C, 07 ...

Page 7

... Datasheet : ADC1020 – C35 OPERATING MODES The modes of operation are summarized in the table bellow, and described in detail as follows. Mode Description 0 Complete Power Down 1 Normal conversion with internally buffered VCM, VREF and Ibias generation 2 Normal conversion with internal VREF and Ibias generation, ...

Page 8

... The converter operates with fully-differential or single-ended inputs. The best performance of this ADC is reached for fully-differential inputs. Single Ended Mode To use the ADC1020 as a Single Ended Converter the input VINN must be connected to VCM. In this case the ADC performs a single-ended to fully-differential conversion. The second input VINP should be balanced around VCM. ...

Page 9

... Datasheet : ADC1020 – C35 FUNCTIONAL BLOCK DIAGRAM MDAC S/H 1 FLASH Clk D8 TIMING DIAGRAM The sampling rate of the AD1020 is defined by the frequency of the CLK signal. The input signal voltage of the ADC is sampled in the falling edge of CLK. As the conversion stages operate in a staggered fashion in alternate phases of CLK, the duty-cycle of this signal must be 50%. The results are latched in the output register on the falling edge of CLK, with a latency of 5 CLK periods ...

Page 10

... Datasheet : ADC1020 – C35 TYPICAL APPLICATION The ADC1020 is targeted for general purpose sampling ADC functions where high-speed conversion rates and medium precision are of critical importance CPK 10uF 100nF 100pF 1.65V Configuration: Op. Mode 1 at 20MS/sec, fully differential with VREF= CPK ...

Page 11

... Datasheet : ADC1020 – C35 Contact austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 support@austriamicrosystems.com Revision C, 07.09.02 Copyright Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner ...

Related keywords