adc1020 austriamicrosystems, adc1020 Datasheet - Page 4

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adc1020

Manufacturer Part Number
adc1020
Description
Cmos 10-bit Pipelined A/d Converter
Manufacturer
austriamicrosystems
Datasheet
Datasheet : ADC1020 – C35
DIGITAL INPUTS AND OUTPUTS
Symbol
VDD
VSS
VIL
VIH
VOL
VOH
B[9:0]
POWER REQUIREMENTS
Symbol
VDDA
VSSA
IDD
IDDA
Psup
Pdiss_tot
IDD
IDDA
Psup
IREF
Pdiss_tot
Pdiss_pd
TIMING CHARACTERISTICS
Symbol
fclk
1/Ts
Jclk
Tsd
Tod
1)
2)
3)
4)
Revision C, 07.09.02
The digital output codes of the ADC are not valid during the first few clock cycles after a power up.
In Op. Mode 1 (internal references) with VREF=1V at 20MHz clock frequency.
In Op. Mode 6 (external references) with VREF=1V at 20MHz clock frequency.
After 10us power down.
1)
2)
1)
2)
2)
1)
2)
1)
2)
3)
Parameter
Pos. digital Supply Voltage
Neg. digital Supply Voltage
Digital Input Level
Digital Output Level
Output Code
Parameter
Pos. analog Supply Voltage
Neg. analog Supply Voltage
Supply Current Digital
Supply Current Analog
Supply Power Consumption
Total Power Dissipation Powerup Mode
Supply Current Digital
Supply Current Analog
Supply Power Consumption
Reference Current
Total Power Dissipation Powerup Mode
Power Consumption
Power Down Mode
Parameter
CLK Frequency
Sampling Rate
CLOCK Jitter
Clock falling edge to sampling instant
delay
Clock falling edge to data out delay
Clock duty cycle
Data Latency
Power Up Delay
4)
Conditions
VDD=VDDA
GND=GNDA
Vind=-VREF
Vind=VREF
Conditions
VDD=VDDA
GND=GNDA
Op. Mode 1
Op. Mode 1
Op. Mode 1
Op. Mode 1
Op. Mode 6
Op. Mode 6
Op. Mode 6
Op. Mode 6
Op. Mode 6
Op. Mode 0
Conditions
Min
1
45
5
Min
2.7
0
GND
0.7VDD
Min
2.7
0
Typ
3.3
0
GND
VDD
000
3FF
Typ
3.3
0
1.5
59
200
200
1.5
38
130
170
131
100
Typ
fclk
1.1
5
50
20
5
Max
3.6
0
0.3VDD
VDD
Max
20
55
5
Max
3.6
0
3
108
400
400
3
69
260
340
261
200
16
*
Page 4 of 11
fin
10
5 −
V
V
V
V
V
HEX
Units
V
HEX
Units
MHz
MS/sec
psec
nsec
nsec
%
CLK cycle
CLK cycle
Units
V
V
mA
mA
mW
mW
mA
mA
mW
µA
mW
µW

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