tda8765h/5 NXP Semiconductors, tda8765h/5 Datasheet - Page 10

• Manufacturer Part Number: tda8765h/5
• Description: 10-bit High-speed Analog-to-digital Converter Adc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
2. It is possible with an external reference connected to pin V
3. The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
7. Output data acquisition: the output data is available after the maximum delay of t
1999 Jan 06
Timing (C
t
t
t
3-state output delay times; see Fig.6
t
t
t
t
d(s)
h
d
dZH
dZL
dHZ
dLZ
10-bit high-speed Analog-to-Digital
Converter (ADC)
SYMBOL
a) PECL mode 1 (DC level varies equal to DC level of V
b) PECL mode 2 (DC level varies equal to DC level of V
c) PECL mode 3 (DC level varies equal to DC level of V
d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with
referenced to V
full-scale sine wave.
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter ( 6 dB
below full scale for each input signal).
d
product.
THD
3
is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
=
L
20 log
= 10 pF); see Fig.5 and note 7
bit
sampling delay time
output hold time
output delay time
enable HIGH
enable LOW
disable HIGH
disable LOW
6.02 + 1.76 dB.
---------------------------------------------------------------------------------------------------------------
CCA
(2nd)
. For V
PARAMETER
2
+
(3rd)
CCA
2
1.825 V, the differential input voltage amplitude is 2 V (p-p).
+
(4th)
F
2
+
(5th)
V
V
CCO
CCO
2
= 5.25 V
= 3.0 V
+
CONDITIONS
(6th)
10
2
CCD
CCD
CCD
ref
): CLK and CLK inputs are at differential PECL levels.
): CLK input is at PECL level and sampling is taken on
): CLK input is at PECL level and sampling is taken on
to adjust the ADC input range. This voltage has to be
4
MIN.
d
.
10
13
14
16
16
14
TYP.
Preliminary specification
2
15
18
18
20
20
18
TDA8765
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
UNIT