tda8025hn NXP Semiconductors, tda8025hn Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
tda8025hn
Manufacturer Part Number
tda8025hn
Description
Ic Card Interface
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8025HN.pdf
(38 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
tda8025hn/C1
Manufacturer:
NXP
Quantity:
490
NXP Semiconductors
TDA8025_1
Product data sheet
8.6 Activation sequence
After the power-on and internal pulse width delay, the microcontroller checks the presence
of the card using signal OFFN.
If the card is in the reader (either pin PRESN or pin PRES is true), the microcontroller can
start a card session by pulling pin CMDVCCN LOW. When using an external crystal, the
following sequence is applied (see
Calculation of the time delays is as follows:
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.
The clock is applied to the card in one of the following ways:
Remark: Do not perform activation with pin RSTIN permanently pulled HIGH.
1. pin CMDVCCN is pulled LOW (t0)
2. the crystal oscillator is triggered
3. the internal oscillator changes to its high frequency (t1)
4. V
5. pins I/O, AUX1 and AUX2 which were pulled LOW are driven HIGH (t3)
6. the clock (pin CLK) is applied to the C3 contact (t4)
7. pin RST is enabled (t5)
25 s. t3 is called t
•
•
•
•
•
•
•
•
•
The card is present when pins OFFN and CMDVCCN are HIGH
The card is not present when pin OFFN is LOW and pin CMDVCCN is HIGH
t1 = t0 + 2.13 ms
t2 = t1
t3 = t1 + 5T/2
t4 = driven by host controller; > t3 and < t5
t5 = t1 + 11T/2
using pin RSTIN: The clock (pin CLK) start-up can be selected at either t3 or t5 using
pin RSTIN. When pin RSTIN is HIGH and pin CMDVCCN is LOW, setting pin RSTIN
to LOW between delays t3 and t5 sends signal CLK. Pin RSTIN should be held LOW
until after delay t5. After passing t5, pin RST is a copy of pin RSTIN and has no further
effect on pin CLK. It enables the microcontroller to precisely choose the CLK start by
counting clock cycles from the falling edge of the RSTIN signal.
not using pin RSTIN: If this feature is not needed, set both pins CMDVCCN and
RSTIN to LOW. The clock (pin CLK) will start at delay t3 (a minimum 200 ns after the
input/output transition). After delay t5, pin RSTIN can be set HIGH to receive the card
Answer To Request (ATR).
CC
rises either from 0 V to 3 V or 1.8 V on a controlled slope (t2)
d(start)
Rev. 01 — 6 April 2009
and t5 is called t
Figure
8):
d(end)
.
TDA8025
© NXP B.V. 2009. All rights reserved.
IC card interface
14 of 38