tda8433 NXP Semiconductors, tda8433 Datasheet - Page 6

• Manufacturer Part Number: tda8433
• Description: Deflection Processor For Computer Controlled Tv Receivers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2 Status register bits
Pin 12 - Positive supply (12 V)
The nominal supply voltage at pin 12
is 12 V which should remain within
the defined limits. The nominal
current consumption is 20 mA.
Pins 13 and 18 - Ground (1 and 2)
Ground 1 (pin 13) is for the bus
transceiver section
Ground 2 (pin 18) is for the sawtooth
and picture geometry control section.
Pins 14 and 15 - SDA and SCL
(serial data and serial clock)
Input serial data is applied to pin 14.
The serial clock input from the
I
Pin 16 - Internal supply voltage
(+5 V)
In some applications it may be
necessary to connect a capacitor to
this pin to avoid interference.
Pin 19 - East-west drive output
The output drive for the East-west
correction circuit has a nominal range
from 1.6 to 11.7 V and contains 5
programmable parameters (see
Fig.5). The parameters are:
August 1991
2
Not locked to computer video
60 Hz transmitter found
50 Hz transmitter found
C-bus is applied to pin 15.
Picture width
East-west raster correction
East-west trapezium correction
East-west corner correction
Compensation for EHT variations
Deflection processor for computer
controlled TV receivers
STATE OF SYNC PROCESSOR
(TDA2579)
Pins 20 and 21 - Vertical drive
output and vertical feedback input
The vertical comparator and drive
output stage is designed so that the
feedback signal applied to pin 21 can
be inverted in the comparator by the
V-out control bit. This enables the use
of two different vertical output stages.
One output stage is without an
internal comparator (e.g. TDA3654).
The feedback signal at pin 21 has a
negative slope during scan. During
power-up the IC is adapted (preset)
for this type of output stage. The other
output stage contains a comparator.
The drive for this output stage is
obtained by interconnecting pins 20
and 21 and switching the V-out
polarity. The V-out bit will then be set
to logic 1. In both cases the drive
signal available at pin 20 contains 5
parameters which can be set via the
I
Pins 22 and 23 - Vertical
sawtooth/vertical amplitude
capacitor
The 100 nF capacitor connected to
pin 22 is charged and discharged by
two current sources in the vertical
ramp generator. In order to obtain an
2
C-bus control;
Picture height
Vertical linearity
Vertical S-correction
Vertical shift
Extent of compensation for EHT
variations (see Fig.4.)
0.7 to 0.75 V
0.7 V(min.)
0.75 V
TYPICAL VOLTAGE AT PIN 11
CC
to V
CC
CC
6
equal amplitude, at different
frequencies, an amplitude
comparator has been incorporated.
The circuit, together with the 330 nF
capacitor connected to pin 23, keeps
the sawtooth amplitude at reference
voltage level (7.1 V). The external
load of the amplitude stabilization
loop of pin 23 should be as low as
possible. The recommended value is
Pin 24 - EHT input (Modulation)
A voltage between 1.7 and 6 V
(depending on the EHT variations)
applied to pin 24 will modulate the
amplitude of the vertical drive
sawtooth and the East-west drive
output. In this way the effect of beam
current variations can be virtually
eliminated.
I
The addresses for the I
100011Ao0 (write) and 100011Ao1
(read). The inclusion of the Ao bit
makes it possible to control two
different deflection processors. After
receiving the address byte the
I
which the status of the control bits is
contained.
PONRES - Power-on-reset
After switch-on, or a power dip below
6.7 V, the PONRES bit is set to logic
1. After a status read operation
PONRES is reset to logic 0.
2
2
C-BUS CONTROL
C-bus transmits its status byte in
500 M .
'1'
'0'
'0'
HLOCKN
STATE OF
Product specification
TDA8433
'0'
'0'
'1'
2
C-bus are
50/60 Hz