pca9558pw NXP Semiconductors, pca9558pw Datasheet - Page 7

• Manufacturer Part Number: pca9558pw
• Description: 8-bit I2c And Smbus I/o Port With 5-bit Multiplexed/1-bit Latched 6-bit I2c Eeprom And 2 K Bit Eeprom
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The GPIOs are controlled by a set of 4 internal registers: Input Port Register (IPR); Output Port Register (OPR); Polarity Inversion Register
(PIR); and the Input/Output Configuration Register (IOCR). Each register is read/write via the I
of the IPR, which is read only, one at a time. The read/write takes place on the slave ACKNOWLEDGE. The control of which register is currently
available to the I
Table 3. Input Port Register (IPR)
This register is an input-only port. It reflects the logic value present
on the GPIO pins regardless of whether they are configured as
inputs or outputs (IOCR). Writes to this register have no effect.
Table 4. Output Port Register (OPR)
This register is an output-only port. It reflects the outgoing logic
levels of the GPIO defined as outputs in the IOCR. Bit values in this
register have no effect on GPIO defined as inputs. In turn, reads
from this register reflect the value stored in the flip-flop controlling
the output, not the actual output value.
Table 5. Polarity Inversion Register (PIR)
This register enables polarity inversion of GPIO defined as inputs by
the IOCR. If a bit in this register is set to a logic 1, the corresponding
GPIO input port is inverted. If a bit in this register is set to a logic 0,
the corresponding GPIO input port is not inverted.
2003 Jun 27
Default
Default
Default
8-bit I
latched 6-bit I
Bit
Bit
Bit
O7
P7
2
I7
0
0
1
C and SMBus I/O port with 5-bit multiplexed/1-bit
2
C-bus is set by bits in the control register. See Tables 3 through 6 for details.
O6
P6
I6
0
0
1
2
O5
P5
I5
0
0
1
C EEPROM DIP switch and 2-kbit EEPROM
O4
P4
I4
0
0
1
O3
P3
I3
0
0
0
O2
P2
I2
0
0
0
O1
P1
I1
0
0
0
O0
P0
I0
0
0
0
7
Table 6. I/O Configuration Register (IOCR)
This register configures the direction of the GPIO pins. If a bit is set
to a logic 1, the corresponding port pin is enabled as an input with a
high impedance output driver. If a bit is set to a logic 0, the
corresponding port pin is enabled as an output.
Examples of Read/Write to these registers can be found in
Figures 9, 10, 15, and 16.
The I/O_OUT_LOW input, when held LOW longer than the time t
will reset the GPIO registers to their default (power-up) values.
A read of the present value of the inputs MUX_INx can be done via
the I
and entering the correct command code. The preset value on the
MUX_INx inputs is latched at the command code ACKNOWLEDGE.
A REPEATED START is then sent with the R/W bit set to a logic 1,
read, and this latched data is read out on the I
11.
Default
Bit
2
C. This is done by addressing the PCA9558 in a write mode
C7
0
2
C6
C-bus or 256 byte EEPROM, with the exception
0
C5
0
C4
0
C3
0
2
C-bus. See Figure
PCA9558
C2
0
Product data
C1
0
C0
0
W
,