pca9561 NXP Semiconductors, pca9561 Datasheet - Page 12

• Manufacturer Part Number: pca9561
• Description: Quad 6-bit Multiplexed I2c Eeprom Dip Switch
• Manufacturer: NXP Semiconductors

1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
2. C
Philips Semiconductors
AC CHARACTERISTICS
NOTES:
2004 May 17
MUX_IN
Select
SYMBOL
t
Quad 6-bit multiplexed I
t
t
t
t
HD;STA
HD;DAT
SU;DAT
SU;STO
the undefined region of the falling edge of SCL.
SU;STA
t
t
f
t
SYMBOL
SYMBOL
HIGH
LOW
BUF
t
SCL
b
C
SP
t
t
r
f
b
= total capacitance of one bus line in pF.
t
t
t
t
PLH
PHL
PLH
PHL
C
SDA
t
t
SCL
R
F
L
MUX_OUT
MUX_OUT
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
P
LOW-to-HIGH transition time
HIGH-to-LOW transition time
LOW-to-HIGH transition time
HIGH-to-LOW transition time
Output rise time
Output fall time
Test load capacitance on outputs
t
BUF
S
t
HD;STA
PARAMETER
t
LOW
2
C EEPROM DIP switch
PARAMETER
PARAMETER
t
t
R
HD;DAT
Figure 10. Definition of timing
t
HIGH
t
F
12
t
SU;DAT
STANDARD-MODE
MIN
250
4.7
4.0
4.7
4.0
4.7
4.0
0
—
—
—
—
0
1
I
2
C-BUS
Sr
MAX
1000
3.45
100
300
400
—
—
—
—
—
—
—
50
MIN.
1.0
1.0
—
—
—
—
—
t
SU;STA
t
HD;STA
IH(min)
20 + 0.1C
20 + 0.1C
FAST-MODE I
LIMITS
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
0
—
—
TYP.
0
of the SCL signal) in order to bridge
1
28
30
10
—
—
—
8
b
b
2
2
t
SP
2
t
SU;STO
C-BUS
MAX
400
300
300
400
0.9
50
—
—
—
—
—
—
—
MAX.
40
15
43
15
—
3
3
PCA9561
Product data sheet
SU00645
P
UNIT
kHz
pF
ns
ns
ns
ns
UNIT
UNIT
ns/V
ns/V
s
s
s
s
s
s
s
pF
ns
ns
ns
ns