pca9646 NXP Semiconductors, pca9646 Datasheet - Page 4

• Manufacturer Part Number: pca9646
• Description: Pca9646 Buffered 4-channel 2-wire Bus Switch
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
PCA9646
Product data sheet
7.1 V
7.2 SCL — clock signal input
7.3 SC0, SC1, SC2, SC3 — clock signal outputs
7.4 SDA, SD0, SD1, SD2, SD3 — data signal inputs/outputs
Refer to
The power supply voltage for the PCA9646 may be any voltage in the range 2.7 V to
5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports
are a percentage of the IC’s power supply, hence noise margin considerations should be
taken into account when selecting an operating voltage.
The clock signal buffer is unidirectional, with this pin acting as the default input. However,
the clock signal direction may be reversed by setting the MSB of the Control register
HIGH. In normal I
signal to the slave. For lowest cost the PCA9646 combines unidirectional buffering of the
clock signal with a bidirectional buffer for the data signal. Clock stretching is therefore not
supported and slave devices that may require clock stretching must be accommodated by
the master adopting an appropriate clocking when communicating with them.
The buffer includes hysteresis to ensure clean switching signals are output, especially
with slow rise times on high capacitively loaded buses.
The clock signal from SCL is buffered through four independent buffers, and the signal is
presented at the four SC0 to SC3 ports. Ports are open-drain type and require external
pull-up resistors.
When the MSB of the control register is set HIGH, the port direction is reversed. The
ANDed result of the selected SC0 to SC3 lines is then used to drive the open-drain output
of the SCL pin.
The data signal buffers are bidirectional. The port (SDA, or any one of SD0 to SD3) which
first falls LOW, will decide the direction of this buffer and ‘lock out’ signals coming from the
opposite side. As the ‘input’ signal continues to fall, it will then drive the open-drain of the
‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of
noise. Ports are open-drain type and require external pull-up resistors.
At some points during the communication, the data direction will reverse—for example,
when the slave transmits an acknowledge (ACK) or responds with its register contents.
During these times, the controlling ‘input’ side will have to rise to V
the ‘lock’, which then allows the ‘output’ side to gain control, and pull (what was) the ‘input’
side LOW again. This will cause a ‘pulse’ on the ‘input’ side, which can be quite long
duration in high capacitance buses. However, this pulse will not interfere with the actual
data transmission, as it should not occur during times of clock line transition (during
normal I
still met.
DD
, V
SS
2
Figure 1 “Simplified block diagram of
C-bus and SMBus protocols), and thus data signal set-up time requirements are
— DC supply pins
All information provided in this document is subject to legal disclaimers.
2
C-bus operations the master device generates a unidirectional clock
Rev. 1 — 1 March 2011
PCA9646”.
Buffered 4-channel 2-wire bus switch
unlock
PCA9646
© NXP B.V. 2011. All rights reserved.
before it releases
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