tda933xh NXP Semiconductors, tda933xh Datasheet - Page 9

• Manufacturer Part Number: tda933xh
• Description: Tda933xh Series I2c-bus Controlled Tv Display Processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
When no horizontal flyback pulse is detected during three
consecutive line periods, status bit NHF is set (output
status byte 01-D3; see Table 3).
The horizontal drive signal is switched on and off via the
so-called slow-start/slow-stop procedure. This function is
realized by varying the t
EHT generators without a bleeder, the IC can be set to a
‘fixed beam current mode’ via bit FBC. In this case, the
picture tube capacitance is discharged with a current of
approximately 1 mA. The magnitude of the discharge
current is controlled via the black current feedback loop.
If necessary, the discharge current can be enlarged with
the aid of an external current division circuit. With the fixed
beam current option activated, it is still possible to have a
black screen during switch-off. This can be realized by
placing the vertical deflection in an overscan position. This
mode is activated via bit OSO.
An additional mode of the IC is the ‘low-power start-up’
mode. This mode is activated when a supply voltage of 5 V
is supplied to the start-up pin.
The required current for this mode is 3 mA (typ.). In this
condition, the horizontal drive signal has the nominal t
and the t
30% of the nominal value. This results in a line frequency
of approximately 50 kHz (2f
signal remains unchanged until the main supply voltage is
switched on and the I
horizontal drive then gradually changes to the nominal
frequency and duty cycle via the slow-start procedure.
The IC can only be switched on and to standby mode when
both standby bits (STB0 and STB1) are changed. The
circuit will not react when only one bit changes polarity.
The IC has a general purpose bus controlled DAC output
with a 6-bit resolution and with an output voltage range
between 0.2 to 4 V. In the TDA9331H, the DC voltage on
this output is proportional to the horizontal line frequency
(only in VGA mode). This voltage can be used to control
the supply voltage of the horizontal deflection stage, to
maintain constant picture width for higher line frequencies.
V
The drive signals for the vertical and E-W deflection
circuits are generated by a vertical divider, which derives
its clock signal from the line oscillator. The divider is
synchronized by the incoming V
input processor or the feature box. The vertical ramp
generator requires an external resistor and capacitor; the
tolerances for these components must be small.
2002 Jun 04
ERTICAL DEFLECTION AND GEOMETRY CONTROL
I
2
C-bus controlled TV display processors
on
grows gradually from zero to approximately
2
C-bus data has been received. The
on
of the horizontal drive pulse. For
H
) or 25 kHz (1f
D
pulse, generated by the
H
). The output
off
9
In the normal mode, the vertical deflection operates in
constant slope and adapts its amplitude, depending on the
frequency of the incoming signal (50 or 60 Hz, or
100 or 120 Hz). When the TDA933xH is switched to the
VGA mode, the amplitude of the vertical scan is stabilized
and independent of the incoming vertical frequency. In this
mode, the E-W drive amplitude is proportional to the
horizontal frequency so that the correction on the screen is
not affected.
The vertical drive is realized by a differential output
current. The outputs must be DC-coupled to the vertical
output stage (e.g. TDA8354).
The vertical geometry can be adjusted via the I
Controls are possible for the following parameters:
With regard to the vertical wait, the following conditions are
valid:
Vertical amplitude
S-correction
Vertical slope
Vertical shift (only for compensation of offsets in output
stage or picture tube)
Vertical zoom
Vertical scroll (shifting the picture in the vertical direction
when the vertical scan is expanded)
Vertical wait, an adjustable delay for the start of the
vertical scan.
In the 1f
and cannot be adjusted with the vertical wait
In the 2f
depends on the value of the Vertical Scan Reference
(VSR) bus bit. If VSR = 0, the start of the vertical scan is
related to the end of the incoming V
it is related to the start. In both cases, the start of the
scan can be adjusted with the vertical wait setting
In the multi-sync mode (TDA9331H and TDA9332H
both in 1f
scan is related to the start of the incoming V
can be adjusted with the vertical wait setting.
H
H
H
TV mode, the start of the vertical scan is fixed
TV mode, the start of the vertical scan
mode and 2f
H
mode), the start of the vertical
TDA933xH series
Preliminary specification
D
pulse. If VSR = 1,
D
2
pulse and
C-bus.