adv7342 Analog Devices, Inc., adv7342 Datasheet - Page 32

• Manufacturer Part Number: adv7342
• Description: Multiformat Video Encoder Six, 11-bit, 297 Mhz Dacs
• Manufacturer: Analog Devices, Inc.

ADV7342/ADV7343
Table 19. Register 0x31 to Register 0x33
SR7 to
SR0
0x31
0x32
0x33
Register
ED/HD Mode
Register 2
ED/HD Mode
Register 3
ED/HD Mode
Register 4
Bit Description
ED/HD Pixel Data Valid.
Reserved.
ED/HD Test Pattern Enable.
ED/HD Test Pattern Hatch/Field.
ED/HD VBI Open.
ED/HD Undershoot Limiter.
ED/HD Sharpness Filter.
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
ED/HD CGMS.
ED/HD CGMS CRC.
ED/HD Cr/Cb Sequence.
Reserved.
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
Reserved.
ED/HD Chroma SSAF.
ED/HD Chroma Input.
ED/HD Double Buffering.
Rev. 0 | Page 32 of 88
7
0
1
0
1
0
1
6
0
0
1
1
0
1
0
1
5
0
1
0
1
0
0
0
0
1
0
1
Bit Number
4
0
1
0
0
1
1
0
0
3
0
1
0
1
0
1
0
0
1
2
0
1
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
Register Setting
Pixel data valid off.
Pixel data valid on.
ED/HD test pattern off.
ED/HD test pattern on.
Hatch.
Field/frame.
Disabled.
Enabled.
Disabled.
−11 IRE
−6 IRE
−1.5 IRE
Disabled.
Enabled.
0 clock cycles.
1 clock cycle.
2 clock cycles.
3 clock cycles.
4 clock cycles.
0 clock cycles.
1 clock cycle.
2 clock cycles.
3 clock cycles.
4 clock cycles.
Disabled.
Enabled.
Disabled.
Enabled.
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC.
Disabled.
Enabled.
Disabled.
Enabled.
4:4:4
4:2:2
Disabled.
Enabled.
0 must be written to these bits.
0 must be written to this bit.
Reset
Value
0x00
0x00
0x68