dac1208d750 NXP Semiconductors, dac1208d750 Datasheet - Page 20

• Manufacturer Part Number: dac1208d750
• Description: Dac1208d750 Dual 12-bit Dac; Up To 750 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1208D750
Product data sheet
10.2.5.4 All slave mode
The external reference is provided by the JESD204A transmitter. All DACs are configured
in slave mode.
The MDS signal is now driven from the transmitter. It is generated at the end of the
inter-lane alignment phase (see the JESD204A standard for details).
The transmitter must also compensate for the DAC latency. Although the DAC has an
internal samples delay line, it cannot handle large delays.
In this mode, PCB layout is also important. The following delay equation applies:
δt < Δt
Fig 11. All slave mode
mds
INSERTION
/A/
< TDAC − δt, where δt is the clock skew considered close to DAC pins.
JESD204A
TX
All information provided in this document is subject to legal disclaimers.
dT
Rev. 2 — 6 December 2010
MDS
SYNC_0
SYNC_1
SYNC_2
DIG
DIG
DIG
2×, 4× or 8× interpolating DAC with JESD204A
ref_A
ref_A
ref_A
BUFFER
BUFFER
BUFFER
MGMT
MGMT
MGMT
COMP
COMP
COMP
CLK
CLK
CLK
mds_out
mds_out
mds_out
mds_in
mds_in
mds_in
Q
Q
Q
I
I
I
DAC
DAC
DAC
DAC1208D750
DISTRIBUTION
CLOCK
© NXP B.V. 2010. All rights reserved.
SLAVE
SLAVE
SLAVE
DAC 0
DAC 1
DAC 2
REF_CLOCK
001aal069
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