dac1408d750 NXP Semiconductors, dac1408d750 Datasheet - Page 95

dac1408d750

Manufacturer Part Number

dac1408d750

Description

Dac1408d750 Dual 14-bit Dac; Up To 750 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface

Manufacturer

NXP Semiconductors

Datasheet

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NXP Semiconductors

Table 60. MAINCONTROL register (address 00h) bit

Table 61. JCLK_CNTRL register (address 03h) bit

Table 62. RST_EXT_FCLK register (address 04h) bit

Table 63. RST_EXT_DCLK register (address 05h) bit

Table 64. DCSMU_PREDIVCNT register (address 06h) bit

Table 65. PLL_CHARGETIME register (address 07h) bit

Table 66. PLL_RUN_IN_TIME register (address 08h) bit

Table 67. CA_RUN_IN_TIME register (address 09h) bit

Table 68. SET_VCM_VOLTAGE register (address 16h) bit

Table 69. SET_SYNC register (address 17h)

Table 70. TYPE_ID register (address 1Bh)

Table 71. DAC_VERSION register (address 1Ch) bit

Table 72. DIG_VERSION register (address 1Dh) bit

Table 73. JRX_ANA_VERSION register (address 1Eh) bit

Table 74. PAGE_ADDRESS register (address 1Fh) bit

Table 75. Lane common-mode voltage adjustment . . . . .55

Table 76. SYNC common-mode voltage adjustment . . . .55

Table 77. SYNC swing voltage adjustment . . . . . . . . . . .55

Table 78. Page 4 register allocation map . . . . . . . . . . . .56

Table 79. SR_DLP_0 register (address 00h)

Table 80. SR_DLP_1 register (address 01h)

Table 81. FORCE_LOCK register (address 02h) bit

Table 82. MAN_LOCK_LN_1_0 register (address 03h) bit

Table 83. MAN_LOCK_2_0 register (address 04h) bit

Table 84. CA_CNTRL register (address 05h)

Table 85. SCR_CNTRL register (address 06h)

Table 86. ILA_CNTRL register (address 07h)

Table 87. FORCE_ALIGN register (address 08h) bit

DAC1408D750

Product data sheet

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bit description . . . . . . . . . . . . . . . . . . . . . . . . .61

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 2 December 2010

Table 88. MAN_ALIGN_LN_0_1 register (address 09h) bit

Table 89. MAN_ALIGN_LN_2_3 register (address 0Ah) bit

Table 90. FA_ERR_HANDLING register (address 0Bh) bit

Table 91. SYNCOUT_MODE register (address 0Ch) bit

Table 92. LANE_POLARITY register (address 0Dh) bit

Table 93. LANE_SELECT register (address 0Eh) bit

Table 94. SOFT_RESET_SCRAMBLER register (address

Table 95. INIT_SCR_S15T8_LN0 register (address 11h) bit

Table 96. INIT_SCR_S7T1_LN0 (address 12h) bit

Table 97. INIT_SCR_S15T8_LN1 register (address 13h) bit

Table 98. INIT_SCR_S7T1_LN1 register (address 14h) bit

Table 99. INIT_SCR_S15T8_LN2 register (address 15h) bit

Table 100. INIT_SCR_S7T1_LN2 register (address 16h) bit

Table 101. INIT_SCR_S15T8_LN3 register (address 17h) bit

Table 102. INIT_SCR_S7T1_LN3 register (address 18h) bit

Table 103. INIT_ILA_BUFPTR_LN01 register (address 19h)

Table 104. INIT_ILA_BUFPTR_LN23 register (address 1Ah)

Table 105. ERROR_HANDLING register (address 1Bh) bit

Table 106. REINIT_CNTRL register (address 1Ch) bit

Table 107. PAGE_ADDRESS register (address 1Fh) bit

Table 108. Page 5 register allocation map . . . . . . . . . . . . 68

Table 109. ILA_MON_1_0 register (address 00h) bit

Table 110. ILA_MON_3_2 register (address 01h) bit

Table 111. ILA_BUF_ERR register (address 02h) bit

Table 112. CA_MON register (address 03h)

Table 113. DEC_FLAGS register (address 04h) bit

2×, 4× or 8× interpolating DAC with JESD204A

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10h) bit description . . . . . . . . . . . . . . . . . . . . . 64

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bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70

DAC1408D750

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