tdf8599c NXP Semiconductors, tdf8599c Datasheet - Page 13

• Manufacturer Part Number: tdf8599c
• Description: I2c-bus Controlled Stereo Class-d Amplifier 136 W/8 With Full Diagnostics
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDF8599C_SDS
Product short data sheet
8.4.2.2 AC load detection (tweeter detection)
8.4.3 CLIP detection
8.4.4 Start-up and shutdown sequence
DC Load detection has built in spike filtering and a door-slam processor to remove
disturbances caused by switching relays in the wiring harness, EMC or the closing of a car
door. Reliable load detection is performed in one diagnostic cycle with these filter
techniques.
AC load detection is only available in I
The default setting for bit IB3[D4] = 0 disables AC load detection. When AC load detection
is enabled (bit IB3[D4] = 1), the amplifier load current is measured and compared with a
reference level. Pin CLIP is activated when this threshold is reached. Using this
information, AC load detection can be performed using a predetermined input signal
frequency and level. The frequency and signal level should be chosen so that the load
current exceeds the programmed current threshold when the AC coupled load (tweeter) is
present.
CLIP detection gives information for clip levels exceeding a threshold defined as the THD
level of a sinusoidal output signal of  0.2 %. In non-I
output for the clip detection circuitry on both channel 1 and channel 2. Setting either bit
IB1[D5] or bit IB2[D5] to logic 0 in I
information on the CLIP pin.
To prevent switch on or switch off ‘pop noises’, a capacitor (C
SVRR is used to smooth start-up and shutdown. During start-up and shutdown, the output
voltage tracks the voltage on pin SVRR. Increasing C
shutdown time. Enhanced pop noise performance is achieved by muting the amplifier until
the SVRR voltage reaches its final value and the outputs start switching. The capacitor
value on pin SEL_MUTE (C
pin SEL_MUTE determines the amplifier gain. Increasing C
mute times. In addition, a larger C
When the amplifier is switched off with an I
the amplifier is first muted and then capacitor (C
In Slave mode, the device enters the off state immediately after capacitor (C
discharged. In Master mode, the clock is kept active by an additional delay (t
approximately 50 ms to allow slave devices to enter the off state.
A clock signal is needed during the start-up and shutdown sequence. When an external
clock is connected to pin OSCIO (in Slave mode), the clock must remain active during the
shutdown sequence for delay (t
to enter the off state. A watchdog is added to protect against clock failure.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 August 2011
ON
) determines the unmute and mute timing. The voltage on
d
(1)
ON
) to ensure that the slaved TDF8599C devices are able
2
C-bus mode defines which channel reports clip
value increases the DC load detection cycle time.
2
C-bus mode and is controlled using bit IB3[D4].
2
C-bus command or by pulling pin EN LOW,
I
2
C-bus controlled stereo class-D amplifier
SVRR
2
) is discharged.
SVRR
C-bus mode pin CLIP is used as the
results in a longer start-up and
ON
SVRR
increases the unmute and
) connected to pin
TDF8599C
© NXP B.V. 2011. All rights reserved.
SVRR
d
(2)
) of
) is
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