adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 30

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
Clock and Reset Timing
Table 16
Absolute Maximum Ratings on Page
CLKIN and clock multipliers must not select core/peripheral
clocks that exceed maximum operating conditions.
Table 16. Clock and Reset Timing
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
Applies to PLL bypass mode and PLL non-bypass mode.
If the DF bit in the PLL_CTL register is set, then the maximum t
CLKIN frequency must not change on the fly.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
CKIN
CKINL
CKINH
WRST
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
and
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
Figure 11
CLKIN
RESET
describe clock and reset operations. Per
1, 2, 3
t
CKINL
t
CKIN
28, combinations of
t
CKINH
4
Rev. A | Page 30 of 60 | February 2008
CKIN
Figure 11. Clock and Reset Timing
period is 50 ns.
t
WRST
Min
20.0
8.0
8.0
11 t
CKIN
Max
100.0
Unit
ns
ns
ns
ns