adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 31

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adsp-bf539bbcz-5f8

Manufacturer Part Number
adsp-bf539bbcz-5f8
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
Asynchronous Memory Read Cycle Timing
Table 17
on Page 32
tions for synchronous and for asynchronous ARDY.
Table 17. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
t
t
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SDAT
HDAT
SARDY
HARDY
DO
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
ARE
ARDY
AOE
DATA15–0
and
describe asynchronous memory read cycle opera-
Table 18 on Page 32
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
SETUP
t
DO
and
Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Figure 12
1
1
and
PROGRAMMED READ ACCESS
t
DO
Rev. A | Page 31 of 60 | February 2008
Figure 13
4 CYCLES
t
SARDY
BE, ADDRESS
t
HARDY
ACCESS EXTENDED
t
SARDY
3 CYCLES
ADSP-BF539/ADSP-BF539F
t
HARDY
Min
2.1
0.8
4.0
0.0
0.8
t
t
HO
SDAT
READ
1 CYCLE
HOLD
Max
6.0
t
HDAT
t
HO
Unit
ns
ns
ns
ns
ns
ns

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