dsp56853 Freescale Semiconductor, Inc, dsp56853 Datasheet - Page 3
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dsp56853
Manufacturer Part Number
dsp56853
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56853.pdf
(60 pages)
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Freescale Semiconductor
56853 General Description
• 120 MIPS at 120MHz
• 12K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program memory or 8M of
• Chip Select Logic for glue-less interface to ROM and
• Six (6) independent channels of DMA
• Enhanced Synchronous Serial Interfaces (ESSI)
• Two (2) Serial Communication Interfaces (SCI)
data memory
SRAM
CS0-CS3[3:0] or
GPIOA0-A3[3:0]
D0-D15 [15:0]
A0-20 [20:0]
WR Enable
RD Enable
Decoding
Peripherals
External Address
External Data
Bus Control
Bus Switch
Bus Switch
12,288 x 16 SRAM
Program Memory
4,096 x 16 SRAM
1024 x 16 ROM
Data Memory
Boot ROM
Interface Unit
External Bus
Memory
Hardware Looping Unit
GPIOE
2 SCI
Program Controller
or
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
4
56853 Technical Data, Rev. 6
56853 Block Diagram
GPIOC
and
ESSI0
or
6
PAB
PDB
CDBR
CDBW
GPIOG
Generation Unit
Timer
Quad
or
Enhanced
Address
4
JTAG/
OnCE
6
IPBus Bridge (IPBB)
GPIOF
SPI
or
4
• Serial Port Interface (SPI)
• 8-bit Parallel Host Interface
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of-Day (TOD)
• 128 LQFP package
• Up to 41 GPIO
Interface
GPIOB
unobtrusive, real-time debugging
Host
V
11
or
DDIO
Three 16-bit Input Registers
16
16 x 16 + 36 → 36-Bit MAC
Four 36-bit Accumulators
IRQA
Controller
Interrupt
6
V
IRQB
DD
Data ALU
System Bus
V
10
SSIO
Control
V
6
56800E Core
SS
Watch-
COP/
dog
V
DDA
16-Bit
Manipulation
V
SSA
Time
COP/TOD CLK
Day
Unit
Bit
of
IPBus CLK
6 channel
DMA
OSC PLL
Generator
Integration
Clock
System
Module
POR
3
RSTO
RESET
CLKO
(GPIOH0-H2)
MODEA-C or
EXTAL
XTAL
3