dsp56857 Freescale Semiconductor, Inc, dsp56857 Datasheet - Page 29

• Manufacturer Part Number: dsp56857
• Description: Dsp56857 Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Freescale Semiconductor
Minimum RESET Assertion Duration
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
IRQA Width Assertion to Recover from Stop State
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
Fast
Normal
normal operation
internal reset mode
RSTO pulse width
1. In the formulas, T = clock cycle. For f
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t
4. This interrupt instruction fetch is visible on the pins only in Mode 3.
5. Fast stop mode:
ed (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less
cycle and t
6. Normal stop mode:
recovery will take an extra cycle (to restart the clock), and t
7. ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.
Operating Conditions: V
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
Operating Conditions: V
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
5
t
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is request-
xtal
6, 7
The PLL is optimized for 4MHz input crystal.
, t
extal
clk
4
will continue with the same value it had before stop mode was entered.
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
or t
osc
7
.
Characteristic
SS
Characteristic
SS
= V
= V
2
SSIO
SSIO
= V
= V
SSA
SSA
3
= 0 V, V
op
= 0 V, V
= 120MHz operation and f
DD
DD
Table 4-6 PLL Timing
56857 Technical Data, Rev. 6
= 1.62-1.98V, V
= 1.62-1.98V, V
1
clk
will resume at the input clock source rate.
Symbol
DDIO
DDIO
f
t
f
osc
plls
Symbol
clk
t
ipb
RSTO
= V
= V
t
t
IRW
t
t
t
RA
IW
IG
IF
= 60MHz, T = 8.33ns.
DDA
DDA
= 3.0–3.6V, T
= 3.0–3.6V, T
Min
40
—
Typ Min
2
128ET
1T + 3
Reset, Stop, Wait, Mode Select, and Interrupt Timing
8ET
18T
30
2T
—
—
clk
A
A
assumes the period of the source clock,
= –40° to +120°C, C
= –40° to +120°C, C
Typ
—
4
1
25ET
Max
Typ
13T
—
—
—
—
—
—
Max
240
L
L
10
Unit
4
≤ 50pF, f
≤ 50pF, f
ns
ns
ns
ns
ns
ns
—
—
1, 2
op
op
See Figure
= 120MHz
= 120MHz
Unit
MHz
MHz
ms
4-10
4-11
4-12
4-13
4-13
4-14
29