dsp56001 Freescale Semiconductor, Inc, dsp56001 Datasheet
dsp56001
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dsp56001 Summary of contents
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... The core of the processor consists of three execution units operating in parallel — the data ALU, the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, com- pact code, straightforward ...
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... ROM 32X24 256X24 YDB XDB PDB GDB PROGRAM PROGRAM DECODE INTERRUPT TWO 56-BIT ACCUMULATORS CONTROLLER CONTROLLER MODB/IRQB MODA/IRQA RESET Figure 1. DSP56001 Block Diagram ADDRESS EXTERNAL ADDRESS BUS SWITCH Y MEMORY RAM 256X24 SINE ROM 256X24 BUS 7 CONTROL EXTERNAL DATA DATA BUS SWITCH ...
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... DMA controller to become the master of external data bus D0-D23 and external address bus A0-A15. When operating mode register (OMR) bit 7 is clear and BR is asserted, the DSP56001 will always re- lease the external data bus D0-D23, address bus A0-A15, and bus control pins PS, DS, X/Y, RD, and WR (i. e., Port A), by placing these pins in the high-impedance state after execution of the current instruc- tion has been completed ...
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... Host Data Bus (H0-H7) This bidirectional data bus is used to transfer data between the host processor and the DSP56001. This bus is an input unless enabled by a host processor read. H0-H7 may be programmed as general pur- pose parallel I/O pins called PB0-PB7 when the Host Interface is not being used ...
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... DSP56001 Electrical Characteristics The DSP is fabricated in high density CMOS with TTL compatible inputs and outputs. Maximum Ratings ( Vdc) SS Rating Supply Voltage All Input Voltages Current Drain per Pin excluding Vcc and V SS Operating Temperature Range Storage Temperature Thermal Characteristics - PGA Package ...
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... User-derived values for thermal resistance may differ. Layout Practices Each Vcc pin on the DSP56001 should be provided with a low-impedance path volts. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive four distinct groups of logic on chip. They are: ...
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... Vcc and Gnd should be kept to less than 1/2" per capacitor lead. A four-layer board is recommended, employing two inner layers as Vcc and Gnd planes. All output pins on the DSP56001 have fast rise and fall times — typically less than 3 ns. with a 10 pf. load. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times ...
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... DSP56001 Electrical Characteristics DC Electrical Characteristics (Vcc = 5.0 Vdc + 10%; T (Vcc = 5.0 Vdc + 5%; T Characteristic Supply Voltage 20 MHz Input High Voltage Except EXTAL, RESET, MODA/IRQA, MODB/IRQB Input Low Voltage Except EXTAL, MODA/IRQA, MODB/IRQB Input High Voltage Input Low Voltage Input High Voltage ...
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... OH AC Electrical Characteristics - Clock Operation The DSP56001 system clock may be derived from the on-chip crystal oscillator as shown in Clock Figure may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected (see Clock Figure 2) to the board or socket. The rise and fall time of this external clock should maximum. ...
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... DSP56001 Electrical Characteristics XTAL R • • C XTAL1 Fundamental Frequency Crystal Oscillator Suggested Component Values For MHz: osc R = 680 20% For MHz: osc R = 680 20% Notes: (1) The suggested crystal source is ICM, # 433163 - 4.00 (4MHz fundamental load 436163 - 30.00 (30 MHz fun- damental load) ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - Reset, Stop, Mode Select and Interrupt Timing (Vcc = 5.0 Vdc +10 -40 to +105° TTL Load at 20.5 MHz and 27 MHz) J (Vcc = 5.0 Vdc + 5 -40 to +105° TTL Load at 33 MHz) J (See Control Figure 1 through 8) ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - Reset, Stop, Mode Select, and Interrupt Timing When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-triggered mode is rec- ommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode. ...
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... While it is possible to set OMR bit when using the internal crystal oscillator not recommended and these specifications do not guarantee timings for that case. See Section 8.5 in the DSP56000/DSP56001 User’s Manual for additional information. 2. Circuit stabilization delay is required during reset when using an external clock in ...
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... DSP56001 Electrical Characteristics EXTAL RESET A0-A15, DS, PS X/Y RESET MODA, MODB Control Figure 3. Operating Mode Select Timing IRQA, IRQB Control Figure 4. External Interrupt Timing (Negative Edge-Triggered) MOTOROLA Control Figure 2. Synchronous Reset Timing 14 V IHM V ILM 16 V IHR IRQA, IRQB ...
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... DSP56001 Electrical Characteristics A0-A15 RD WR IRQA IRQB General Purpose I/O IRQA IRQB Control Figure 5. External Level-Sensitive Fast Interrupt Timing DSP56001 First Interrupt Instruction Execution First Interrupt Instruction Execution General Purpose I/O MOTOROLA 15 ...
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... DSP56001 Electrical Characteristics EXTAL IRQA, IRQB A0-A15, DS PS, X/Y Control Figure 6. Synchronous Interrupt and Synchronous Wait State Timing IRQA A0-A15, DS, PS, X/Y Control Figure 7. Recovery from Stop State Using IRQA IRQA A0-A15, DS, PS, X/Y Control Figure 8. Recovery from Stop State Using IRQA Interrupt Service ...
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... Synchronization of Status Bits from DSP to Host HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF (refer to DSP56000/DSP56001 User’s Manual , I/O Interface section, Host/ DMA Interface Programming Model for descriptions of these status bits) status bits are set or cleared from inside the DSP and read by the Host processor ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - Host I/O Timing (Vcc = 5.0 Vdc + 10 -40 to +105° TTL Load at 20.5 MHz and 27 MHz) J (Vcc = 5.0 Vdc + 5 -40 to +105° TTL Load at 33 MHz) J (see Host Figures 1 through 6) cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles tHSDL = Host Synchronization Delay Time Active low lines should be “ ...
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... Notes: 1. “Host synchronization delay (tHSDL)” is the time period required for the DSP56001 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the DSP56001 internal clock. 2. See HOST PORT USAGE CONSIDERATIONS. 3. HREQ is pulled resistor. ...
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... DSP56001 Electrical Characteristics HREQ (OUTPUT) HACK (INPUT) HR/W (INPUT) H0-H7 (OUTPUT) Host Figure 2. Host Interrupt Vector Register (IVR) Read MOTOROLA Data Valid DSP56001 ...
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... DSP56001 Electrical Characteristics HREQ (OUTPUT) HEN (INPUT) HA2-HA0 (INPUT) HR/W (INPUT H0-H7 (OUTPUT) Host Figure 3. Host Read Cycle (Non-DMA Mode) DSP56001 32A RXH RXM Read Read Address Address Valid Valid Data Data Valid Valid 49 47 RXL Read Address ...
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... DSP56001 Electrical Characteristics HREQ (OUTPUT) TXH HEN Write (INPUT Address HA2-HA0 Valid (INPUT) 39 HR/W (INPUT) 33 H0-H7 (INPUT) Host Figure 4. Host Write Cycle (Non-DMA Mode) HREQ (OUTPUT) 45 HACK RXH (INPUT) Read 36 35 H0-H7 (OUTPUT) MOTOROLA 22 TXM Write 32 44 Address Valid 40 34 Data Data Valid ...
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... DSP56001 Electrical Characteristics HREQ (OUTPUT HACK TXH (INPUT) Write 33 H0-H7 (INPUT) DSP56001 46 32 TXM Write 34 Data Data Valid Valid Host Figure 6. Host DMA Write Cycle 46 46 TXL Write Data Valid MOTOROLA 23 ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - SCI Timing (Vcc = 5.0 Vdc + 10 -40 to +105° TTL Load at 20.5 MHz and 27 MHz, J Vcc = 5.0 Vdc + 5 -40 to +105° TTL Load at 33 MHz, J see SCI Figures 1 and 2) cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles tSCC = Synchronous Clock Cycle Time (for internal clock tSCC is determined by the SCI clock control register and Icyc ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - SCI Timing (Vcc = 5.0 Vdc + 10 -40 to +105° TTL Load at 20.5 MHz and 27 MHz, J Vcc = 5.0 Vdc + 5 -40 to +105° TTL Load at 33 MHz, J see SCI Figures 1 and 2) cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles ...
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... DSP56001 Electrical Characteristics INTERNAL CLOCK SCLK (OUTPUT) 59 TXD RXD EXTERNAL CLOCK SCLK (INPUT) TXD RXD MOTOROLA DATA VALID 61 DATA VALID DATA VALID 65 DATA VALID SCI Figure 1. SCI Synchronous Mode Timing DSP56001 ...
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... DSP56001 Electrical Characteristics 1X SCK (OUTPUT) TXD Note: In the wire-OR mode, TXD can be pulled SCI Figure 2. SCI Asynchronous Mode Timing DSP56001 DATA VALID 70 MOTOROLA 27 ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - SSI Timing (Vcc = 5.0 Vdc + 10 -40 to +105° TTL Load at 20.5 MHz and 27 MHz, J Vcc = 5.0 Vdc + 5 -40 to +105° TTL Load at 33 MHz, J see SSI Figures 1 and 2) cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - SSI Timing (Continued) Note: 1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register. Characteristics Num 93 Flags Input Setup Before RXC Falling Edge 94 Flags Input Hold Time After RXC Falling Edge 95 TXC Rising Edge to FST Out (bl) High ...
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... DSP56001 Electrical Characteristics 83 RXC (Input/Output) FSR (Bit) OUT FSR (Word) OUT DATA IN FSR (Bit) IN FSR (Word) IN FLAGS IN MOTOROLA First SSI Figure 1. SSI Receiver Timing 87 89 Bit Last Bit 92 94 DSP56001 ...
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... DSP56001 Electrical Characteristics 83 81 TXC (Input/Output) FST (Bit) OUT FST (Word) OUT DATA OUT 102 FST (Bit) IN FST (Word) IN FLAGS OUT Note the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period ...
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... Clock cycle = 1/2 instruction cycle = 2 T cycles WS = Number of Wait States, Determined by BCR Register ( 15) The DSP56001 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pf, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates linearly per additional capacitance from 250 pf of loading ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - External Bus Asynchronous Timing Characteristics Num 127 Address Valid deassertion WS > 0 128 Input Data Hold Time to RD Deassertion 129 RD Assertion Width 130 Address Valid to Input Data Valid 131 Address Valid to RD Assertion 132 RD Assertion to ...
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... DSP56001 Electrical Characteristics BR BG A0-A15, PS, DS, X/Y, RD, WR D0-D23 Async. Bus Figure 1. Bus Request / Bus Grant Timing A0-A15, DS, PS, X/Y (See Note 1) RD 120 135 WR 123 D0-D23 Note: 1. During Read-Modify-Write instructions and internal instructions, the address lines do not change state. Async. Bus Figure 2. External Bus Asynchronous Timing ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - External Bus Synchronous Timing Vcc = 5.0 Vdc + 10 -40 to 105° 20.5 MHz 27 MHz J Vcc = 5.0 Vdc + 5 -40 to 105° MHz J Num Characteristics 140 Clk Low Transition To Address Valid 141 Clk High Transition Assertion (see Note 2) WS > ...
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... DSP56001 Electrical Characteristics T0 CLK in A0-A15 DS,PS X/Y 140 RD 141 WR D0-D23 Sync. Bus Figure 1. DSP56001 Synchronous Bus Timing Note: During Read-Modify-Write Instructions, the address lines do not change states. MOTOROLA 143 142 Data Out 145 149 144 147 148 Data In 146 ...
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... DSP56001 Electrical Characteristics AC Electrical Characteristics - Bus Strobe / Wait Timing Characteristics Num 150 Clk Low Transition To BS Assertion 151 WT Assertion To Clk Low Transition (setup time) 152 Clk Low Transition To WT Deassertion For Minimum Timing 153 WT Deassertion To Clk Low Transition For Maximum Timing (2 wait states ...
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... PS, DS, X/Y 150 BS 151 WT 143 RD D0-D23 141 WR D0-D23 Bus Arbitration Figure 1. DSP56001 Synchronous Timings Note: During Read-Modify-Write Instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. MOTOROLA 152 153 147 ...
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... BS 156 WT 131 RD 23 D0-D 120 WR D0-D23 Bus Arbitration Figure 2. DSP56001 Asynchronous Timings Note: During Read-Modify-Write Instructions, the address lines will not change states. However, BS will deassert before asserting again for the write cycle. DSP56001 157 123 125 Data Out 160 159 ...
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... DSP56001 Electrical Characteristics MOTOROLA 40 DSP56001 ...
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... One housing sub-assembly and one cover are required for each socket. DSP56001 APPENDIX A ORDERING INFORMATION Frequency 20 = 20.5 MHz MHz MHz. DSP Type 56001 = RAM Part DSP56001 SOCKET INFORMATION PGA Socket Type Part Number Standard 88 Pin 4CS088-01TG Standard 88 Pin 1-916223-3 1-55283-9 Standard 128 Pin ...
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... PER ANSI Y14.5M. 1982. 1.380 0.120 2. CONTROLLING DIMENSION: INCH. 0.022 0.200 X SC1 SRD STD SC2 GND VCC SCK SC0 SCLK GND TXD H0 RXD H2 H1 HREQ HEN HR MATRIX PINS DSP56001 G ...
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... NMI/MODB/IRQB 88 120 D23 87 119 D22 86 118 D21 85 117 NO CONNECT 84 Note: Do not connect to “NO CONNECT” pins. “NO CONNECT” pins are reserved for future enhancements. DSP56001 PIN # FUNCTION NO CONNECT 83 NO CONNECT D20 82 D1 D19 81 D0 D18 80 A15 DATA BUS GND 79 A14 ...
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... Mechanical Specification Figure A-2. Ceramic Quad Flat Pack MOTOROLA A-44 DSP56001 ...
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... Mechanical Specification Figure A-2. Ceramic Quad Flat Pack (Continued) DSP56001 MOTOROLA A-45 ...
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... Mechanical Specification Figure A-3. Plastic Quad Flat Pack MOTOROLA A-46 DSP56001 ...
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... Mechanical Specification Figure A-3. Plastic Quad Flat Pack (Continued) DSP56001 MOTOROLA A-47 ...
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... The lowest cost DSP56001 based system is shown in Figure uses no run time external memory and requires only two chips, the DSP56001 and a low cost EPROM. The EPROM read access time should be less than 780 nanoseconds when the DSP56001 is operating at a clock rate of 20.5 MHz. ...
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... Figure B-3 shows the DSP56001 bootstrapping via the Host Port from an MC68000. Systems with external program memory can load the on-chip PRAM without using the bootstrap mode. In Figure B-4, the +5 V 15K 15K 15K FROM OPEN COLLECTOR BUFFER FROM RESET FUNCTION FROM OPEN ...
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... DLY 8. 20.5 MHz osc Notes: 1. IRQA and IRQB must be hardwired. 2. MODA and MODB must be hard wired. XTAL EXTAL 10 pf +5V • R RESET • C DLY • DLY 2 0 20% DLY DSP56001 ...
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... A13 6 A14 7 A15 Figure B-7. 27 MHz DSP56001 with 20 ns SRAM DSP56001 into the ranges X:$1000-1FFF and Y:$1000-1FFF. The PLD < 10 ns, equation is: DW RAM_ENABLE = PS & !DS & !A15 & !A14 & !A13 & !A12 RAM_ENABLE 12 MCM6264D ( DATA ADDRESS ...
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... Figure B-8 shows the DSP56001 connected to the bus of an IBM-PC computer. The PAL equations and other details of this circuit are available in “An ISA BUS INTERFACE FOR THE NOTE: CONNECTOR ISA BUS All Series Resistors 15K OHMS IRQA IRQB OSC B30 A04 ...
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... M_39 DC $0ABC00 M_3A DC $0A3C00 M_3B DC $09BC00 M_3C DC $093C00 M_3D DC $08BC00 M_3E DC $083C00 Figure C-1. Mu-Law/A-Law Expansion Table Contents (Sheet DSP56001 APPENDIX C M_3F M_40 ; 8031 M_41 ; 7775 M_42 ; 7519 M_43 ; 7263 M_44 ; 7007 M_45 ; 6751 M_46 ; 6495 M_47 ; 6239 M_48 ...
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... DC $062000 ; 196 DC $06E000 ; 220 DC $06A000 ; 212 DC $02B000 ; 86 DC $029000 ; 82 DC $02F000 ; 94 DC $02D000 ; 90 DC $023000 ; 70 DC $021000 ; 66 DC $027000 ; 78 DC $025000 ; 74 DC $03B000 ; 118 DC $039000 ; 114 DC $03F000 ; 126 DC $03D000 ; 122 DC $033000 ; 102 DC $031000 ; 98 DC $037000 ; 110 DC $035000 ; 106 DSP56001 ...
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... This sine wave table is normally used by FFT routines which use bit reversed address pointers. This table can be used for up to 512 point FFTs; however, for larger FFTs, the table must be copied to a different memory location to allow the reverse-carry address- ing mode to be used (see Section 5.3.2.3 REVERSE-CARRY MODIFIER (Mn=$0000) in the DSP56000/DSP56001 Digital Signal Processor User’s Manual for additional information). ...
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... S_E8 DC $B8E313 ; -0.5555701852 S_E9 DC $BB8533 ; -0.5349975824 S_EA DC $BE31E2 ; -0.5141026974 S_EB DC $C0E8B6 ; -0.4928981960 S_EC DC $C3A946 ; -0.4713967144 S_ED DC $C67323 ; -0.4496113062 S_EE DC $C945E0 ; -0.4275551140 S_EF DC $CC210D ; -0.4052414000 S_F0 DC $CF043B ; -0.3826833963 S_F1 DC $D1EEF6 ; -0.3598949909 S_F2 DC $D4E0CB ; -0.3368898928 S_F3 DC $D7D947 ; -0.3136816919 S_F4 DC $DAD7F4 ; -0.2902846038 DSP56001 ...
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... S_F6 DC $E0E607 ; -0.2429800928 S_F7 DC $E3F47E ; -0.2191012055 S_F8 DC $E70748 ; -0.1950902939 S_F9 DC $EA1DEC ; -0.1709619015 S_FA DC $ED37F0 ; -0.1467303932 Figure D-1. Sine Wave Table Contents (Sheet DSP56001 S_FB DC $F054D9 ; -0.1224106997 S_FC DC $F3742D ; -0.0980170965 S_FD DC $F69570 ; -0.0735644996 S_FE DC $F9B827 ; -0.0490676016 S_FF DC $FCDBD5 ; -0.0245412998 MOTOROLA D-57 ...
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... ROM into program memory space as long as the DSP56001 remains in Operating Mode 1. The bootstrap firm- ware changes operating modes when the bootstrap load is com- pleted. When the DSP56001 exits the reset state in Mode 1, the following actions occur. 1. The control logic maps the bootstrap ROM into the inter- nal DSP program memory space starting at location $0000 ...
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... SET L FLAG = 1 (INDICATES A BOOT FROM EXTERNAL MEMORY WAS SELECTED) START DO LOOP , 512 ITERATIONS N REPEAT UNTIL 512 PROGRAM WORDS HAVE BEEN LOADED Figure E-1. Bootstrap Program Flowchart DSP56001 LOAD FROM HOST IS INTERFACE Y L FLAG =0? LOAD FROM EXTERNAL N MEMORY DO 3 TIMES (GET 8-BIT DATA ...
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... BOOTSTRAP SOURCE CODE FOR DSP56001 - (C) Copyright 1986 Motorola Inc Host algorithm / AND / external bus method 6 ; This is the Bootstrap source code contained in the DSP56001 32 word boot ROM This program can load the internal program memory from one of two external sources The program reads P:$C000 bit 23 to decide which external source to access ...
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... This is the first routine. It loads from external P: memory P:000C 060380 000010 Figure E-2. Assembler Listing for Bootstrap Program (Sheet DSP56001 ORI #$40,CCR ; Set the L bit to indicate ; that the bootstrap program ; is being loaded from the ; external P: space. D0 #512,_LOOP1 ; Load 512 instruction words. ...
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... Store 24-bit result in PRAM. ; and return for another 24-bit word MOVEC #2,0MR ; Set the operating mode (and trigger an exit from ; bootstrap mode). ANDI #$0,CCR ; Clear RESET and ; introduce delay needed for ; Op. Mode change. JMP <$0 ; Start fetching from PRAM P:$0000 DSP56001 ...
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... DSP56001 MOTOROLA E-63 ...
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