saa7110 NXP Semiconductors, saa7110 Datasheet - Page 7

• Manufacturer Part Number: saa7110
• Description: One Chip Front-end 1 Ocf1
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1995 Oct 18
RESET
CGCE
V
V
HCL
HSY
HS
PLIN (HL)
ODD (VL)
VS
HREF
V
V
SYMBOL
DD
SS
SS
DD
One Chip Front-end 1 (OCF1)
PIN
32
33
34
35
36
37
38
39
40
41
42
43
44
Reset active LOW input/output (CGCE = 1, output; CGCE = 0, input); sets the device into a
defined state. All data outputs are in high impedance state. The I
START condition). Using the external CGC, the LOW period must be maintained for at least
30 LLC clock cycles.
CGC Enable active HIGH input (CGCE = 1, on-chip CGC active; CGCE = 0, external CGC
mode, use SAA7197).
supply voltage (+5 V)
ground
Horizontal Clamping input/output pulse (programmable via I
output; PULIO = 0, input). This signal is used to indicate the black level clamping period for
the analog input interface. The beginning and end of its HIGH period (only in the output mode)
can be programmed via the I
17H in 60 Hz mode, active HIGH.
Horizontal Synchronization input/output indicator (programmable via I
PULIO = 1, output; PULIO = 0, input). This signal is fed to the analog interface. The beginning
and end of its HIGH period (only in the output mode) can be programmed via the I
registers 01H, 02H in 50 Hz mode and registers 14H, 15H in 60 Hz mode, active HIGH.
Horizontal Synchronization output (programmable; the HIGH period is 128 LLC clock cycles).
The position of the positive slope is programmable in 8 LLC increments over a complete line
(64 s) via the I
PAL Identifier Not output; marks for demodulated PAL signals the inverted line (PLIN = LOW)
and a non-inverted line (PLIN = HIGH) and for demodulated SECAM the DR line
(PLIN = LOW) and the DB line (PLIN = HIGH). Select PLIN function via I
(H-PLL locked output; a HIGH state indicates that the internal PLL has locked. Select HL
function via I
ODD/EVEN field identification output; a HIGH state indicates the odd field. Select ODD
function via I
(Vertical Locked output; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)
is in a locked state. Select VL function via I
Vertical Synchronization input/output (programmable via I
output; OEHV = 0, input). This signal indicates the vertical synchronization with respect to the
YUV output. The high period of this signal is approximately six lines if the VNL function is
active. The positive slope contains the phase information for a deflection controller, for
example the TDA9150. In input mode this signal is used to synchronize the vertical gain and
clamp blanking stage, active HIGH.
Horizontal Reference output; this signal is used to indicate data on the digital YUV-bus. The
positive slope marks the beginning of a new active line. The HIGH period of HREF is either
768 Y samples or 640 Y samples long depending on the detected field frequency
(50/60 Hz mode). HREF is used to synchronize data multiplexer/demultiplexers. HREF is also
present during the vertical blanking interval.
ground
supply voltage (+5 V)
2
2
C-bus bit RTSE = 1).
C-bus bit RTSE = 0.
2
C-bus register 05H in 50 Hz mode or register 18H in 60 Hz mode.
2
C-bus registers 03H, 04H in 50 Hz mode and registers 16H,
7
DESCRIPTION
2
C-bus bit RTSE = 1).
2
C-bus bit OEHV: OEHV = 1,
SAA7110; SAA7110A
2
C-bus bit PULIO: PULIO = 1,
2
C-bus is reset (waiting for
2
C-bus bit PULIO:
2
C-bus bit RTSE = 0.
Product specification
2
C-bus