saa7103h-v4 NXP Semiconductors, saa7103h-v4 Datasheet - Page 17

• Manufacturer Part Number: saa7103h-v4
• Description: Digital Video Encoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
The input vertical offset can be taken from the assumption that the scaler should just have
finished writing the first line when the encoder starts reading it:
In most cases the vertical offsets will be the same for odd and even fields. The results
should be rounded down.
Once the timings are known the scaler can be programmed.
XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX ≤ HLEN is fulfilled.
Values given by the VESA display timings are preferred.
HLEN = InPpl − 1
XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.
YPIX = InLin
YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum
vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth.
When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not
be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added
and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE
positive.
TPclk
TPclk
PCL
YOFS
XPIX
XINC
YINC
YIWGTO
YIWGTE
=
=
=
=
=
=
=
TXclk
-------------- -
TPclk
InPix
------------- -
-----------------------
InLin
OutPix
------------------
----------------------------------------------------------------------------------------- -
InPpl
----------------------------------------------------------------------------------------- -
InPpl
FAL
-------------------------------------------------- - 2
InPix
OutLin
=
=
2
InPpl TPclk
YINC YSKIP
-------------------------------------
YINC
------------- -
×
×
2
+
×
×
1716
2
262.5 1716
312.5 1728
×
2
integer
integer
21
×
–
×
4096
+
2
(all frequencies); see
⎛
⎝
2048
×
1
Rev. 04 — 18 January 2006
×
×
TXclk
+
⎛
⎝
⎛
⎝
YSKIP
---------------- -
InLin
-----------------------
InLin
-----------------------
4095
OutLin
OutLin
×
×
–
TXclk
TXclk
⎞
⎠
+
+
×
(60 Hz)
2
2
4096
×
×
262.5
312.5
YOFS
Table
⎞
⎠
⎞
⎠
(60 Hz)
(50 Hz) and for the pixel clock generator
SAA7102; SAA7103
74.
=
FAL
-------------------------------------------------- - 2
InPpl TPclk
×
1728
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
×
×
TXclk
Digital video encoder
–
(50 Hz)
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