saa7157 NXP Semiconductors, saa7157 Datasheet - Page 3

• Manufacturer Part Number: saa7157
• Description: Clock Signal Generator Circuit For Digital Tv Systems Scgc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The SAA7157 generates all clock signals required for a
digital TV system suitable for the SAA715x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder (DMSD2) and video
enhancement and D/A processor circuit (VEDA). Optional
extras (feature box, video memory etc.) can be driven via
external buffers, advantageous for a digital TV system
based on display standard conversion concepts.
The 6.75 MHz input signal LFCO (triangular waveform)
coming from the DMSD or LFCO2 is multiplied to 27 MHz
by the PLL (including phase detector, loop filter, VCO and
frequency divider) and output on LL1.5A (pin 7) and
LL1.5B (pin 10). The 13.5 MHz frequencies are generated
by dividers using ratio of 1:2 and are output on LL3A (pin
14) and LL3B (pin 20).
The rectangular output signals have 50% duty factor.
Outputs with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available before the PLL has locked-on.
May 1992
handbook, full pagewidth
Clock signal generator circuit for digital TV
systems (SCGC)
LFCO2
LFCO
MS
CE
11
19
2
1
PRE-FILTER
DETECTOR
SHAPER
FILTER
PHASE
PULSE
LOOP
AND
MS = LOW
Fig.1 Block diagram.
16
SAA7157
LFCOSEL
V DDA
FREQUENCY
POWER-ON
DIVIDER
5
RESET
3
VCO
1 : 2
Mode select MS
The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.
Source select LFCOSEL
Line frequency control signal (LFCO) is selected by
LFCOSEL input.
LFCOSEL = LOW:
signal from LFCO (pin 11) is selected.
LFCOSEL = HIGH:
signal from LFCO2 (pin 19) is selected.
This function is not tested.
Chip enable CE
The buffer outputs are enabled and RESN is set to HIGH
by
CE = HIGH (Fig.4).
CE = LOW sets the clock outputs HIGH and RESN output
LOW.
3
PORD
V DDD1 V DDD2
8
4
V SSA
FREQUENCY
DIVIDER
17
DELAY
1 : 2
6, 9, 13, 18
V SSD
MEH452
10
14
20
15
12
7
Product specification
LL1.5A
(LL27A)
LL1.5B
(LL27B)
LL3A
LL3B
CREF
RESN
SAA7157