saa7191b NXP Semiconductors, saa7191b Datasheet - Page 11

• Manufacturer Part Number: saa7191b
• Description: Digital Multistandard Colour Decoder, Square Pixel Dmsd-sqp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.2
The luminance input signal, a digital CVBS format or an
8-bit luminance format (S-VHS, Hi8), is fed through a
sample rate converter to reduce the data rate to
14.75 MHz for PAL and SECAM (12.2727 MHz for NTSC),
Fig.4.
Sample rate is converted by means of a switchable
pre-filter. High frequency components are emphasized to
compensate for loss in the following chrominance trap
filter. This chrominance trap filter (f
f
most of the colour carrier signal, therefore, it must be
by-passed for S-Video (S-VHS and Hi8) signals.
The high frequency components of the luminance signal
can be “peaked” (control for sharpness improvement via
the I
characteristic.
A coring circuit with selectable characteristic improves the
signal once more, this signal is then added to the original
(“unpeaked”) signal. A switchable amplifier achieves a
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the variable delay
compensation.
7.3
The delay from input to output is 220 LLC cycles if YDEL
is set to 0. The processing delay will be influenced in future
enhancements.
7.4
The luminance output signal is fed to the synchronization
stage. Its bandwidth is reduced to 1 MHz in a low-pass
filter. The sync pulses are sliced and fed to the phase
detectors to be compared with the sub-divided clock
frequency.
The resulting output signal is applied to the loop filter to
accumulate all phase deviations. Adjustable output signals
(e. g. HCL and HSY) are generated according to peripheral
requirements (TDA8708A, TDA8709A). The output signals
HS, VS and PLIN are locked to the timing reference signal
HREF (Figures 7 and 8). There is no absolute timing
reference guaranteed between the input signal and the
HREF signal as further improvements to the circuit may
change the total processing delay. It is therefore not
recommended to use them for applications, which ask for
absolute timing accuracy to the input signals.
The loop filter signal drives an oscillator to generate the
line frequency control output signal LFCO.
August 1996
o
= 3.58 MHz centre frequency selectable) eliminates
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
2
C-bus) in two bandpass filters with selectable transfer
Luminance processor
Processing delay
Synchronization
o
= 4.43 MHz or
11
Table 1 Clock frequencies in MHz for 50/60 Hz systems
7.5
LFCO is required in an external PLL (SAA7197) to
generate the line locked clock frequency.
7.6
The 16-bit YUV-bus transfers digital data from the output
interfaces to a feature box, or to the digital-to-analog
converter (DAC). Outputs are controlled via the I
normal selections, or they are controlled by output enable
chain (FEIN on pin 64, Fig.5). The YUV-bus data rate
equals LLC2 in Table 1. Timing is achieved by marking
each second positive rising edge of the clock LLC in
conjunction with CREF (clock reference).
YUV-bus formats 4:2:2 and 4:1:1
The output signals Y7 to Y0 are the bits of the digital
luminance signal. The output signals UV7 to UV0 are the
bits of the multiplexed colour-difference signals (B Y) and
(R Y). The frame in the following tables is the time,
required to transfer a full set of samples. In case of 4 : 2 : 2
format two luminance samples are transmitted in
comparison to one U and one V sample within one frame.
LLC
LLC2
LLC4
LLC8
CLOCK
Line locked clock frequency
YUV-bus, digital outputs
29.5
14.75
7.375
3.6875
50 Hz
Product specification
SAA7191B
24.545454
12.272727
6.136136
3.068181
60 Hz
2
C-bus in