saa7167 NXP Semiconductors, saa7167 Datasheet - Page 9

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saa7167

Manufacturer Part Number
saa7167
Description
Yuv-to-rgb Digital-to-analog Converter Dac
Manufacturer
NXP Semiconductors
Datasheet

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Table 8 Bit functions in data byte; notes 1 and 2
Notes
1. All I
2. PCLK should be active in any event to allow for correct operation of I
DC CHARACTERISTICS
T
1995 Nov 03
FMTC1 and FMTC0
KINV
KEN
DRP
KMOD2 to KMOD0
KDLY2 to KDLY0
KD7 to KD0
V
V
I
V
V
V
V
V
V
DNL
INL
amb
DDtot
DDD
DDA
IH
IL
IH
IL
in
out
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SYMBOL
= 0 to 70 C.
2
C-bus control bits are initialized to logic 0 after RES is activated.
BIT
digital supply voltage
analog supply voltage
total supply current (f
HIGH level input voltage (pin SDA)
LOW level input voltage (pin SDA)
HIGH level digital input voltage
LOW level digital input voltage
full-scale analog RGB inputs
full scale analog RGB outputs (for 150
differential non-linearity error of video output
integral non-linearity error of video output
video format control:
key polarity:
key enable:
UV input data code: 0 = two’s complement; 1 = binary offset
keying mode:
added keying delay cycles (from 0 to 7 PCLK)
the data value compared for 8, 16 or 24-bit pixel colour key
00; YUV 4 : 2 : 2
01; YUV 4 : 1 : 1
10; YUV 2:1:1/CCIR 656
11; RGB 5 : 6 : 5
KINV = 0: EXTKEY = HIGH for analog mixer to select DAC outputs
KINV = 1: EXTKEY = HIGH for analog mixer to select analog RGB inputs
0 = disable
1 = enable
000; external key
100; 8-bit pixel colour key
101; 2
110; 2
111; 3
all other combinations are reserved
PARAMETER
clk
= 50 MHz)
8-bit pixel colour key (with two-edge clock latching for pixel input)
8-bit pixel colour key (with one-edge clock latching for pixel input)
8-bit pixel colour key (with one-edge clock latching for pixel input)
9
load)
DESCRIPTION
2
C-bus programming.
4.75
4.75
3
2
0.5
MIN.
5.0
5.0
100
0.7
1.4
TYP.
Preliminary specification
5.25
5.25
V
+1.5
0.8
1
1
DDD
MAX.
+ 0.5
SAA7167
V
V
mA
V
V
V
V
V
V
LSB
LSB
UNIT

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