saa7207h NXP Semiconductors, saa7207h Datasheet - Page 7

• Manufacturer Part Number: saa7207h
• Description: Reed Solomon Decoder Ic
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Synchronization (see Fig.4)
The input stream is interpreted as a stream of bytes
consisting of blocks which;
Both de-interleaving and Reed Solomon decoding are
based on this block structure. Energy dispersal
descrambling is based on frames consisting of 8 blocks.
The first block of a frame has a sync byte of B8H, and the
remaining 7 blocks have a sync byte of 47H.
Consequently, there are 2 synchronization processes:
1. Synchronization process 1: handles byte alignment
2. Synchronization process 2: handles frame
With reference to note 2 in Fig 4, BERR is asserted at the
beginning of each new RS word (rising edge of BEGIN).
NOSYNC = 0 when 6 consecutive sync bytes have been
detected. BERR = 0 when the beginning of a frame has
been detected (de-scrambler lock) and not more than
8 bytes were wrong. When more than 8 bytes are wrong,
the BERR stays at logic 1 during the length of the word.
De-interleaving (see Fig.5)
Input data is interleaved, conforming a convolutional
interleaving scheme. If we describe a Reed Solomon block
as a 0 to 203 one dimensional byte array then;
Reed Solomon decoder
The IC contains a high throughput Reed Solomon decoder
consisting of three fully pipelined hardware units that
execute finite field computations on de-interleaved input
data blocks with lengths of 204 bytes.
1996 Jul 17
Have a fixed 204 byte length
Start with 1 synchronization byte.
Interleaving means that byte N of each block
(N = 0 to 203) has been delayed by exactly D1 blocks
(D1 = N mod 12)
So to de-interleave byte N of each block (N = 0 to 203)
has to be delayed by D2 blocks [D2 = (203-N) mod 12].
Reed Solomon decoder IC
and block synchronization. It is based on a state
machine running from state 0 (out of sync) to state 6
(fully synchronized).
synchronization for de-scrambling. It is based on the
detection of a B8H sync byte (after Reed Solomon
correction). Whenever such a sync byte is detected at
the beginning of a correct/corrected block, a free
running ‘block of frame counter’ is
synchronized/resynchronized.
7
Each of the units is dedicated to one of the following
decoder algorithm stages;
1. Power sum polynomial (syndrome) calculation
2. Execution of the Euclidean algorithm to find the error
3. Execution of a Chien search to find the roots of the
Code generator polynomial:
g (X) = (X + L0), (X + L1), (X + L2) to (X + L15)
where L = 02H
Field generator polynomial:
Error correction
The error correction unit corrects the errors as calculated
by the Reed Solomon unit if, and only if, they are
correctable. If not, the block is sent to the output
unmodified (i.e. as received). If ‘Transport Error Indicator’
(TEI = first bit after sync byte) modification is enabled the
error flag is set in all uncorrectable blocks.
In all cases the 16 parity bytes are stripped (the output is
set to zero; BCLK is stopped) from the block reducing it to
188 bytes length.
De-randomizing
The energy dispersal descrambling algorithm is based on
a 15 bit shift register which is initialised upon the arrival of
the Least Significant Bit (LSB) of the first byte of each
frame. De-scrambling is disabled for all sync bytes.
Output interface (see Fig.6)
The output data stream consists of a sequence of bytes
(BYTEO 7 is the MSB). A new byte is present at the output
pins at each rising edge of the byte clock. The BEGIN
output is asserted for the first byte of a block and negated
elsewhere. The BERR output is asserted during
uncorrectable and/or unsynchronized blocks and negated
during correct/corrected blocks.
p X
locator polynomial and the error evaluator polynomial
error locator polynomial. For each root the error value
is calculated (Forney algorithm) and stored in memory.
=
X8
+
X4
+
X3
+
X2
+
1
Product specification
SAA7207H