saa7274 NXP Semiconductors, saa7274 Datasheet - Page 7

• Manufacturer Part Number: saa7274
• Description: Audio Digital Input Circuit Adic
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 3 Subcode generation
Table 4 Channel status
Notes
1. copy permitted.
2. pre-emphasis.
If the value of the category bits does not equal 10000000 (compact disc format) and the value of the mode bits equals
00 (mode 0), then:
Additional input and output signals
The following input and output signals are available from this circuit:
July 1991
series 1,
series 2,
series 3,
and after receiving the next user byte:
series 4,
1
control
Generates the following subcodes:
If the value of the category bits, bits 9 to 16 of the input signal, = 10000000 (compact disc format) and the value of the
mode bits, bits 7 and 8, = 00, the user data output (OSDU) will deliver the bits of the subcode following the specified
lay-out (above). The subcode starts only after receipt of at least 16 zero bits. Simultaneously a user clock signal
(OSCU) consisting of 10 clock pulses is present. The output signal starts when a subcode is completed and is clocked
on the negative transition of OSCU. The first data word of each subcode frame is output 3 times in succession with the
data pattern shifted each time as outlined for series 1 through series 3 in the layout given above. The CRC performs
a check on the 96 Q bits of the preceding subcode. If CRC is correct then the CRC bit = 1.
Channel status:
output OSDU indicates the status of bit 4 (pre-emphasis) of the channel status and output
OSCU indicates the status of bit 3 (copy permitted) of the channel status provided the control bits conform to the
2-channel audio signal format.
Uses the output pre-emphasis (OPRE) to indicate the status of bit 4 of the channel status for a 2-channel audio signal.
Outputs the 4 control bits of the biphase input signal (IBIFA) represented by V, U, C and P at OCDB. The output
delivers the bits in the same sequence during the next word, each bit continues for 32 clock pulses.
Phase output signal (OPHA) and phase reference signal (OREF) for use in a phase-locked loop (PLL). The OPHA
signal is a result of the difference between the frequency and phase of the biphase input signal and the system clock.
OREF signal provides the reference signal for the PLL.
Input signal IFDEN enables the frequency detector. The frequency detection as present in the 2 signals OPHA and
OREF can be enabled by making this signal LOW.
Data clock output signal (ODCL), which has a frequency of 1/4 of the system clock frequency.
Word clock output signal (OWSY), which has a frequency of 1/256 of the system clock frequency.
Block synchronization output signal (OBSY), which has a frequency of 1/49152 of the system clock.
ODCL, OWSY and OBSY will be synchronized to the block preambles in the biphase input signal IBIFA.
Audio Digital Input Circuit (ADIC)
2
3
.
0
CRC
0
0
(1)
4
.
(2)
0
0
0
0
5
res
U1
V1
W1
W2
6
.
T1
U1
V1
V2
7
mode
S1
T1
U1
U2
8
R1
S1
T1
T2
9
category
Q1
R1
S1
S2
10
7
1
Q1
R1
R2
11
0
1
Q1
Q2
12
0
0
1
1
13
etc.
14
15
16
Product specification
SAA7274
.
.
.