saa7715ah-n102 NXP Semiconductors, saa7715ah-n102 Datasheet - Page 13

• Manufacturer Part Number: saa7715ah-n102
• Description: Saa7715ah Digital Signal Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.6
The I
to use it” , order no. 9398 393 40011.
For the external control of the SAA7715AH a fast I
is implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are two different types of control instructions:
The detailed description of the I
of the different bits in the memory map is given in
Chapter 9.
8.7
The reset (pin DSP_RESET) is active LOW and needs an
external 22 k pull-up resistor. Between this pin and the
V
allow a proper switch-on of the supply voltage. The
capacitor value is such that the chip is in reset as long as
the power supply is not stabilized. A more or less fixed
relationship between the DSP reset and the POM time
constant is obligatory. The voltage on pin POM determines
the current flowing in the DACs.
2003 Mar 13
handbook, full pagewidth
SSI
Loading of the Program RAM (PRAM) with the required
DSP program
– Programming the coefficient RAM (YRAM)
– Instructions to control the DSP program.
Selection of the digital serial input/output format to be
used, the DSP clock speed.
Digital Signal Processor
t
t
A
A
ground a capacitor of 1 F should be connected to
2
= 4
= 4
C-bus format is described in “The I
I
Reset
2
C-bus interface (pins SCL and SDA)
(256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz.
(512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz.
Power-down mode
device actually in
POWERDOWN
CLK_IN
2
POM
C-bus and the description
2
C-bus and how
Fig.4 Power-down mode.
2
t A
C-bus
t
t
B
B
= 128
= 128
13
The reset sets all I
restarts the DSP program.
8.8
The Power-down mode switches off all activity on the chip.
The Power-down mode can be switched on and off using
pin POWERDOWN. This pin needs to be connected to
ground if not used. The following applies for the
Power-down mode:
Figure 4 shows the time the chip actually is in Power-down
mode after switching on/off pin POWERDOWN.
Power-down mode may only be switched on when there
is no I
Power-down mode may not be switched on before the
complete chip has been reset (DSP_RESET
active LOW)
The clock signal on pin CLK_IN should be running
during Power-down mode
It is advised to set pin POM to logic 0 before switching
on the Power-down mode and set it back to logic 1 after
the chip actually returns from Power-down mode as
shown in Fig.4
All on-chip registers and memories will keep their values
during Power-down mode
Digital serial outputs are not muted, the last value is kept
on the output
The SAA7715AH will not ‘lock-up’ the I
Power-down mode (SDA line).
(256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz.
(512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz.
Power-down mode
2
C-bus activity to or from the SAA7715AH
2
C-bus bits to their default value and it
t B
MGT828
Preliminary specification
SAA7715AH
2
C-bus during