saa7715ah-n102 NXP Semiconductors, saa7715ah-n102 Datasheet - Page 26

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saa7715ah-n102

Manufacturer Part Number
saa7715ah-n102
Description
Saa7715ah Digital Signal Processor
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
15 I
Table 20 Timing of the I
2003 Mar 13
handbook, full pagewidth
f
t
t
t
t
t
t
t
t
t
t
C
t
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
f
SU;STO
SP
SDA
SCL
b
Digital Signal Processor
SYMBOL
2
C-BUS TIMING
t f
S
t HD;STA
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition; after this
period, the first clock pulse
is generated
SCL LOW period
SCL HIGH period
set-up time for a repeated
START condition
DATA hold time
DATA set-up time
rise time of both SDA and
SCL signals
fall time of both SDA and
SCL signals
set-up time for STOP
condition
capacitive load for each
bus line
pulse width of spikes to be
suppressed by input filter
t LOW
PARAMETER
2
C-bus (see Fig.8)
t r
t HD;DAT
t SU;DAT
t HIGH
Fig.8 Timing of the I
C
C
CONDITIONS
t f
b
b
in pF
in pF
t SU;STA
26
0
4.7
4.0
4.7
4.0
4.7
0
250
4.0
not applicable
STANDARD MODE
Sr
2
MIN.
C-bus.
I
2
C-BUS
t HD;STA
100
1000
300
400
MAX.
t SP
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
20 + 0.1C
0.6
0
FAST MODE I
t SU;STO
MIN.
Preliminary specification
b
b
t r
SAA7715AH
400
0.9
300
300
400
50
P
2
MAX.
C-BUS
t BUF
MSC610
S
kHz
ns
ns
ns
pF
ns
UNIT
s
s
s
s
s
s
s

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