ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 111

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 4–26. Read/Write Clock Mode in Simple Dual-Port Mode
Note to
(1)
Altera Corporation
February 2005
All registers shown except the rden register have asynchronous clear ports.
wraddress[ ]
Figure
address[ ]
byteena[ ]
outclken
wrclock
rdclock
inclken
data[ ]
wren
rden
4–26:
8 LAB Row
Clocks
8
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block is less than or equal to
2K bits in size.
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Write Address
Byte Enable
Read Enable
Write Enable
Memory Block
Stratix GX Device Handbook, Volume 1
Note (1)
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
D
ENA
Q
Stratix GX Architecture
Figure
To MultiTrack
Interconnect
4–27. A single
4–45