ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 26

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–13. Receiver PLL & CRU Circuit
Note to
(1)
2–16
Stratix GX Device Handbook, Volume 1
Dedicated
Local
REFCLKB
Global Clks, IO Bus, Gen Routing
Inter Transceiver Routing (IQ2)
m = 8, 10 16, or 20.
Low-Speed TX_PLL_CLK
Figure
2–13:
÷ 2
rx_locktorefclk
rx_locktodata
The receiver PLLs and CRUs are capable of supporting up to 3.1875 Gbps.
The input clock frequency for –5 and –6 speed grade devices is limited to
650 MHz if you use the REFCLKB pin or 325 MHz if you use the other
clock routing resources. The maximum input clock frequency for –7 speed
grade devices is 312.5 MHz if you use the REFCLKB pin or 156.25 MHz
with the other clock routing resources. An optional RX_LOCKED port
(active low signal) is available to indicate whether the PLL is locked to the
reference clock. The receiver PLL has a programmable loop bandwidth,
which can be set to low, medium, or high. The loop bandwidth parameter
can be statically set by the Quartus II software.
Table 2–5
the parameters listed are statically programmable in the Quartus II
software.
Input reference frequency range
Data rate support
Table 2–5. Receiver PLL & CRU Adjustable Parameters (Part 1 of 2)
RX_IN
lists the adjustable parameters of the receiver PLL and CRU. All
RX CRUCLK
Parameter
Receiver PLL
PFD
÷ m (1)
down
down
up
up
CRU
rx_locked
and Loop Filter
Charge Pump
500 Mbps to 3.1875 Gbps
25 MHz to 650 MHz
Specifications
VCO
Altera Corporation
rx_freqlocked[]
rx_riv[ ]
High-speed RCVD_CLK
Low-speed RCVD_CLK
June 2006