ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 255

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
June 2006
Drive Strength
Table 6–80. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers
V
C C I O
Parameter
Parameter
level
voltage
Conditions
Conditions
Conditions
Class II
Class I
24 mA
16 mA
12 mA
Value
Value
8 mA
4 mA
2 mA
3.3 V
2.5 V
The scaling factors for output pin timing in
of time per pF unit of capacitance (ps/pF). Add this delay to the
combinational timing path for output or bidirectional pins in addition to
the “I/O Adder” delays shown in
Programmable Delays” in
3.3-V LVTTL
SSTL-3
GTL+
GTL+/GTL/CTT/PCI Standards
15
25
30
50
60
25
25
18
15
LVTTL/LVCMOS Standards
–
SSTL/HSTL Standards
2.5-V LVTTL
SSTL-2
GTL
Output Pin Adder Delay (ps/pF)
18
25
35
75
Output Pin Adder Delay (ps/pF)
25
20
Output Pin Adder Delay (ps/pF)
18
18
–
–
Tables 6–78
1.8-V LVTTL
Tables 6–72
SSTL-1.8
Stratix GX Device Handbook, Volume 1
CTT
120
25
40
25
25
25
–
–
–
and 6–79.
-
DC & Switching Characteristics
Table 6–80
through
1.5-V LVTTL
1.5-V HSTL
160
PCI
35
80
25
20
20
–
–
-
-
are shown in units
6–77
and the “IOE
1.8-V HSTL
LVCMOS
AGP
15
20
30
60
25
20
20
8
–
-
6–53