ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 21

• Manufacturer Part Number: ep2sgx60e
• Description: 4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Notes to
(1)
(2)
(3)
(4)
(5)
Write enable
Write disable
Read status
Read bytes
Read silicon ID
Write status
Write bytes
Erase bulk
Erase sector
Read Device
Identification
Table 4–15. Operation Codes for Serial Configuration Devices
Operation
The MSB is listed first and the least significant bit (LSB) is listed last.
The status register, data or silicon ID are read out at least once on the DATA pin and will continuously be read out
until nCS is driven high.
Write bytes operation requires at least one data byte on the DATA pin. If more than 256 bytes are sent to the device,
only the last 256 bytes are written to the memory.
Read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64.
Read Device Identification operation is available only for EPCS128.
Table
(5)
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
4–15:
(4)
Operation Code
0000 0100
0000 0101
0000 0011
1010 1011
0000 0001
0000 0010
1100 0111
1101 1000
1001 1111
0000 0110
must drive nCS high after the last bit of the operation sequence is shifted
in.
supported by the serial configuration devices.
For the read byte, read status, and read silicon ID operations, the
shifted-in operation sequence is followed by data shifted out on the
DATA pin. You can drive the nCS pin high after any bit of the data-out
sequence is shifted out.
For the write byte, erase bulk, erase sector, write enable, write disable,
and write status operations, drive the nCS pin high exactly at a byte
boundary (drive the nCS pin high a multiple of eight clock pulses after the
nCS pin is driven low); otherwise, the operation is rejected and is not
executed.
All attempts to access the memory contents while a write or erase cycle is
in progress will not be granted, and the write or erase cycle will continue
unaffected.
Table 4–15
(1)
Address Bytes
shows the operation sequence for every operation
0
0
0
3
0
0
3
0
3
0
Dummy Bytes
0
0
0
0
3
0
0
0
0
2
Configuration Handbook, Volume 2
1 to infinite
1 to infinite
1 to infinite
1 to infinite
1 to 256
Data Bytes
0
0
1
0
0
(3)
(2)
(2)
(2)
(2)
DCLK f
(MHz)
25
25
25
20
25
25
25
25
25
25
MAX
4–21