ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 33

• Manufacturer Part Number: ep2sgx60e
• Description: 4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
• Manufacturer: Altera Corporation

Figure 4–16. Erase Sector Operation Timing Diagram
Note to
(1)
Power and
Operation
Altera Corporation
May 2008
Address bit A[23] is a don't-care bit in EPCS64. Address bits A[23..21] are don't-care bits in EPCS16. Address
bits A[23..19] are don't-care bits in EPCS4. Address bits A[23..17] are don't-care bits in EPCS1.
DCLK
ASDI
nCS
Figure
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
4–16:
0
1
Immediately after the device drives nCS high, the self-timed erase sector
cycle is initiated. Refer to t
cycle time for the respective EPCS devices. You must account for this
amount of delay before the memory contents can be accessed.
Alternatively, you can check the write in progress bit in the status register
by executing the read status operation while the erase cycle is in progress.
The write in progress bit is 1 during the self-timed erase cycle and 0 when
it is complete. The write enable latch bit in the status register resets to 0
before the erase cycle is complete.
This section describes the power modes, power-on reset (POR) delay,
error detection, and initial programming state of serial configuration
devices.
Power Mode
Serial configuration devices support active power and standby power
modes. When nCS is low, the device is enabled and is in active power
mode. The FPGA is configured while in active power mode. When nCS is
high, the device is disabled but could remain in active power mode until
all internal cycles have completed (such as write or erase operations). The
serial configuration device then goes into stand-by power mode. The I
parameter specifies the V
power mode and the I
is in stand-by power mode (refer to
2
Operation Code
3
4
5
6
CC0
7
MSB
parameter specifies the current when the device
23
CC
ES
8
supply current when the device is in active
in
22
Table 4–23
9
24-Bit Address (1)
Table
Configuration Handbook, Volume 2
4–29).
for the self-timed erase sector
3
28
2
29
1
30
0
31
4–33
CC1