ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 36

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ep2sgx60e

Manufacturer Part Number
ep2sgx60e
Description
4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Timing Information
Figure 4–18. Read Operation Timing
4–36
Configuration Handbook, Volume 2
DCLK
DATA
Note to
(1)
t
t
ASDI
EB
ES
nCS
Table 4–23. Write Operation Parameters (Part 2 of 2)
(1)
Symbol
(1)
These parameters are not shown in
Add_Bit 0
Table
4–23:
Erase bulk cycle time for EPCS1
Erase bulk cycle time for EPCS4
Erase bulk cycle time for EPCS16
Erase bulk cycle time for EPCS64
Erase bulk cycle time for EPCS128
Erase sector cycle time for EPCS1, EPCS4,
EPCS16, and EPCS64
Erase sector cycle time for EPCS128
t
nCLK2D
Bit N
Figure 4–18
device's read operation.
Table 4–24
read operation.
f
t
t
RCLK
CH
CL
Table 4–24. Read Operation Parameters (Part 1 of 2)
Symbol
Parameter
Figure
Bit N
defines the serial configuration device timing parameters for
shows the timing waveform for the serial configuration
1
4–17.
Read clock frequency (from
FPGA or embedded processor)
for read bytes operation
DCLK
DCLK
high time
low time
Parameter
Min
t
CL
t
CH
105
Min
Typ
17
68
25
25
3
5
2
2
Bit 0
Altera Corporation
Max
Max
160
250
10
40
20
6
3
6
May 2008
t
ODIS
MHz
Unit
Unit
ns
ns
s
s
s
s
s
s
s

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