ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 31

• Manufacturer Part Number: ep2sgx60e
• Description: 4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
• Manufacturer: Altera Corporation

Figure 4–14. Write Bytes Operation Timing Diagram
Notes to
(1)
(2)
Altera Corporation
May 2008
DCLK
ASDI
nCS
Address bit A[23] is a don't-care bit in EPCS64. Address bits A[23..21] are don't-care bits in EPCS16. Address
bits A[23..19] are don't-care bits in EPCS4. Address bits A[23..17] are don't-care bits in EPCS1.
For RPD files, write the LSB of the data byte first.
Figure
0
1
2
Operation Code
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
3
4–14:
4
5
6
7
MSB
23
8
22
9
If more than 256 data bytes are shifted into the serial configuration device
with a write bytes operation, the previously latched data is discarded and
the last 256 bytes are written to the page. However, if less than 256 data
bytes are shifted into the serial configuration device, they are guaranteed
to be written at the specified addresses and the other bytes of the same
page are unaffected.
If the design must write more than 256 data bytes to the memory, it needs
more than one page of memory. Send the write enable and write bytes
operation codes followed by three new targeted address bytes and
256 data bytes before a new page is written.
nCS must be driven high after the eighth bit of the last data byte has been
latched in. Otherwise, the device will not execute the write bytes
operation. The write enable latch bit in the status register is reset to 0
before the completion of each write bytes operation. Therefore, the write
enable operation must be carried out before the next write bytes
operation.
The device initiates the self-timed write cycle immediately after nCS is
driven high. Refer to t
for the respective EPCS devices. Therefore, you must account for this
amount of delay before another page of memory is written. Alternatively,
you can check the status register’s write in progress bit by executing the
read status operation while the self-timed write cycle is in progress. The
write in progress bit is set to 1 during the self-timed write cycle, and 0
when it is complete.
Erase Bulk Operation
The erase bulk operation code is b'1100 0111, with the MSB listed first.
The erase bulk operation sets all memory bits to 1 or 0xFF. Similar to the
write bytes operation, the write enable operation must be executed prior
to the erase bulk operation so that the write enable latch bit in the status
register is set to 1.
21
10
24-Bit Address (1)
3
28
2
29
1
30
0
31
MSB (2)
7
32
6
33
5
34
Data Byte 1
4
35
WB
3
36
in
2
37
1
Table 4–23
38
0
39
MSB (2)
7
40
6
41
5
42
Data Byte 2
4
43
for the self-timed write cycle time
Configuration Handbook, Volume 2
3
44
2
45
1
46
0
47
MSB (2)
2072 2073 2074 2075 2076 2077 2078 2079
7
6
5
Data Byte 256
4
3
2
1
0
4–31