xc3s1000-5fgg900i Xilinx Corp., xc3s1000-5fgg900i Datasheet - Page 51

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xc3s1000-5fgg900i

Manufacturer Part Number
xc3s1000-5fgg900i
Description
Spartan-3 Fpga Family
Manufacturer
Xilinx Corp.
Datasheet
DS099-2 (v2.5) December 4, 2009
Product Specification
R
Figure 28: Boundary-Scan Configuration Flow Diagram
No
No
and V
(JTAG port becomes
Load configuration
and V
INIT_B = High?
(Clock five 1's
Load JSTART
Load CFG_IN
Reconfigure?
Synchronous
configuration
data frames
User mode
V
instruction
Power-On
Yes
instruction
TAP reset
sequence
CCO
mode pins
Yes
Yes
available)
on TMS)
Start-Up
correct?
CCINT
memory
Sample
CCAUX
Clear
CRC
Bank 4 > 1V
>1V
> 2V
Yes
No
www.xilinx.com
No
INIT_B goes Low.
Abort Start-Up
Shutdown
sequence
Yes
Set PROG_B Low
after Power-On
PROG_B = Low
Spartan-3 FPGA Family: Functional Description
No
JShutdown
instruction
Load
DS099_27_041103
51

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