xc2vp2 Xilinx Corp., xc2vp2 Datasheet - Page 102
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xc2vp2
Manufacturer Part Number
xc2vp2
Description
Virtex-ii Pro And Virtex-ii Pro X Platform Fpgas
Manufacturer
Xilinx Corp.
Datasheet
1.XC2VP2.pdf
(430 pages)
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Table 37: Output Delay Measurement Methodology
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI
HSTL, Class III & IV, with DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III & IV, 1.8V, with DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI
SSTL, Class I & II, 2.5V, with DCI
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
C
Measured as per PCI specification.
Measured as per PCI-X specification.
REF
is the capacitance of the probe, nominally 0 pF.
R
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
HSTL_III_DCI_18, HSTL_IV_DCI_18
HSTL_I_DCI_18, HSTL_II_DCI_18
SSTL18_I_DCI, SSTL18_II_DCI
SSTL2_I_DCI, SSTL2_II_DCI
HSTL_III_DCI, HSTL_IV_DCI
HSTL_I_DCI, HSTL_II_DCI
IOSTANDARD
LVDSEXT_25
LVPECL_25
BLVDS_25
GTLP_DCI
SSTL18_II
SSTL18_I
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
Attribute
SSTL2_II
LVDS_25
GTL_DCI
SSTL2_I
LDT_25
R
(Ω)
1M
1M
1M
1M
1M
1M
50
25
50
25
50
50
50
50
50
50
50
50
50
50
50
REF
C
(pF)
REF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)
V
V
V
V
V
V
V
V
V
V
V
V
1.23
1.65
1.25
0.75
MEAS
(V)
1.2
0.9
0.9
1.1
0.8
1.0
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Module 3 of 4
V
1.25
1.25
0.75
1.25
(V)
0.9
0.9
1.2
1.2
0.6
1.5
0.9
1.8
0.9
1.2
1.5
REF
0
0
0
0
0
0
31
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