xc3100 Xilinx Corp., xc3100 Datasheet
xc3100
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xc3100 Summary of contents
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... DC Characteristics ........................................... 2-171 Switching Characteristic Guidelines CLB .............................................................. 2-172 Buffer ........................................................... 2-172 IOB .............................................................. 2-174 Ordering Information ........................................ 2-176 Component Availability ..................................... 2-176 XC3100, XC3100A Logic Cell Array Families ....... 2-177 Absolute Maximum Ratings ............................. 2-178 Operating Conditions ....................................... 2-178 DC Characteristics ........................................... 2-179 Switching Characteristic Guidelines CLB .............................................................. 2-180 Buffer ........................................................... 2-180 IOB .............................................................. 2-182 Ordering Information ...
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... The ease-of-use of the XC3000A family makes it the obvious choice for all new designs that do not require the speed of the XC3100 or the 3-V operation of the XC3000L. XC3000L Family The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3 ...
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... Features • Complete line of five related Field Programmable Gate Array product families – XC3000, XC3000A, XC3000L, XC3100, XC3100A • Ideal for a wide range of custom VLSI design tasks – Replaces TTL, MSI, and other PLD logic – Integrates complete sub-systems into a single package – ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families The XC3000 Logic Cell Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades. Architecture The perimeter of configurable IOBs provides a pro- grammable interface between the internal logic array and the device package pins ...
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Read or Write Data Figure 2. Static Configuration Memory Cell loaded with one bit of configuration program and controls one program selection in the Logic Cell Array. The memory cell outputs Q and Q use ground and V ...
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... IOB output buffers provide CMOS-compatible 4-mA source-or-sink drive for high fan-out CMOS or TTL- com- patible signal levels ( the XC3100 family). The network driving IOB pin O becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB) pin FT can control output activity ...
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Configurable Logic Block The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. The XC3020 has 64 such blocks arranged in 8 ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Any Function Variables Any Function Variables Any Function Variables Any Function Variables Any Function ...
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RD which, when enabled and High, is dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops’ ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Figure 8. XACT Development System Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line nondirectional interconnection. D:H-> ...
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Figure 9. LCA General-Purpose Interconnect. Composed of a grid of metal segments that may be intercon- nected through switch matrices to form networks for CLB and IOB inputs and outputs ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Figure 12. XC3020 Die-Edge IOBs. The XC3020 die-edge IOBs are provided with direct access to adjacent CLBs. 2-114 X2660 ...
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Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND func- tion. A logic High on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables the buffer to drive the Longline Low. See Figure 15b ...
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Each horizontal Longline is also driven by a weak keeper circuit that prevents undefined floating levels by maintaining the pre- vious logic level when the line is not driven by an active buffer ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Suggested Component Values R1 0.5 – – (may be required for low frequency, phase)t (shift and/or compensation level for crystal Q) C1 – – 20 MHz AT-cut parallel resonant 44 PIN 68 PIN ...
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Figure 18 shows the state sequences. At the end of Initialization, the LCA device enters the Clear state where it clears the configuration memory. The active ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Clear or Configure states. They and DONE/PROG provide signals for control of external logic signals such as RESET, bus enable or PROM enable during configuration. For parallel Master configuration modes, these signals pro- vide PROM enable control and allow the data pins to be shared with user logic signals ...
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DIN Preamble Length Count The configuration data consists of a composite * 40-bit preamble/length count, followed by one or more concatenated LCA programs, separated by 4-bit postambles. An additional final postamble bit is added for each slave device and ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options in the MakeBits program allow timing choices of one clock earlier or later for the timing of the end of the internal logic RESET and the assertion of the DONE signal ...
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IOB pull- up resistors in the Operational mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of a Logic ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Serial Mode * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 DURING CONFIGURATION THE PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ALLOWS USER I/O. GENERAL- PURPOSE USER I/O PINS RESET Figure 21. Master Serial Mode ...
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Master Serial Mode Programming Switching Characteristics CCLK (Output) 1 Serial Data In Serial DOUT n – 3 (Output) Description CCLK Data In setup Data In hold Notes power-up, V must rise from 2 delayed ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Parallel Mode * * + Readback is Activated, a 5-kΩ Resistor is M0 M1PWRDWN Required in Series With M1 5 kΩ CCLK DOUT M2 HDC RCLK A15 General- A14 Purpose User I/O A13 Pins A12 Other A11 I/O Pins LCA ...
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Master Parallel Mode Programming Switching Characteristics A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description RCLK To address valid To data setup To data hold RCLK High RCLK Low Notes power-up, V must rise from 2.0 V ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Peripheral Mode CONTROL ADDRESS SIGNALS BUS +5 V REPROGRAM Figure 23. Peripheral Mode. Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead LCA ...
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Peripheral Mode Programming Switching Characteristics WRITE TO LCA WS, CS0, CS1 CS2 D0-D7 CCLK RDY/BUSY DOUT Description Write Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required DIN Hold time required RDY/BUSY delay after end ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Slave Serial Mode Micro Computer STRB D0 D1 I/O D2 Port RESET Figure 24. Slave Serial Mode. In Slave Serial mode, an external signal drives the CCLK input(s) of the LCA device(s). The serial configuration bitstream must be available at the DIN input of the lead LCA device a short set-up time before each rising CCLK edge ...
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Slave Serial Mode Programming Switching Characteristics DIN 1 T DCC CCLK DOUT (Output) Description CCLK To DOUT DIN setup DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit of CCLK Low time is caused by ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families General LCA Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description RESET (2) M0, M1, M2 setup time required M0, M1, M2 hold time required RESET Width (Low) req. for Abort DONE/PROG Width (Low) required for Re-config ...
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Performance Device Performance The XC3000 families of FPGAs can achieve very high performance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. • Careful optimization of transistor ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 26. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 100 XC3100-3 50 XC3000-125 0 CLB Levels: 4 CLBs 3 CLBs 2 CLBs Gate Levels: (4-16) (3-12) (2-8) Figure 27. Clock Rate as a Function of Logic Complexity ...
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... Different from the XC3000 family which can be powered down to a current consumption of a few microamps, the XC3100 draws 5 mA, even in power-down. This makes power-down operation less meaningful. In contrast, I for the XC3000L is only force the Logic Cell Array into the Powerdown state, the ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Descriptions Permanently Dedicated Pins Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN A Low on this CMOS-compatible input stops all internal activity, but retains configuration ...
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User I/O Pins that can have special functions. M2 During configuration, this input has a weak pull-up resistor. Together with M0 and M1 sampled before the start of configuration to establish the configuration mode to be used. After ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Configuration Mode <M2:M1:M0> SLAVE MASTER-SER PERIPHERAL <1:1:1> <0:0:0> <1:0:1> PWRDWN (I) PWRDWN (I) PWRDWN (I) VCC VCC VCC M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M0 (HIGH) (I) M0 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) M2 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) HDC (HIGH) ...
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XC3000 Families Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 223. Each chip is offered in several package types to ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. XC3030 1 GND 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 PWRDWN 8 TCLKIN-I/O 9 I/O 10 I/O 11 I/O 12 VCC 13 I/O 14 I/O 15 I/O 16 M1-RDATA 17 M0-RTRIG 18 M2-I/O 19 HDC-I/O 20 LDC-I/O 21 I/O 22 INIT-I/O Peripheral mode and Master Parallel mode are not supported in the PC44 package XC3000, XC3000A, XC3000L and XC3100 families have identical pinouts Pin No ...
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... XC3000 Families 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts 68 PLCC XC3020 XC3030 XC3020 XC3030, XC3042 10 10 PWRDN 11 11 TCLKIN-I/O 12 — I/O — — I/O — VCC 19 19 I/O — ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3064/XC3090/XC3195 84-Pin PLCC Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PLCC Pin Number XC3064, XC3090, XC3195 12 PWRDN 13 TCLKIN-I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 GND 22 VCC 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 ...
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... XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. XC3020 TQFP XC3030 CQFP PQFP XC3042 VQFP GND A13-I A6-I A12-I A7 A11-I A8-I A10-I A9-I VCC* ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000 Families 132-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts XC3042 PGA Pin PGA Pin XC3064 Number Number GND C4 B13 A1 PWRDN C11 C3 I/O-TCLKIN A14 ...
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... XC3000 Families 144-Pin Plastic TQFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts XC3042 Pin XC3064 Number 1 PWRDN 2 I/O-TCLKIN 3 I/O* 4 I/O 5 I/O 6 I/O* 7 I/O 8 I/O 9 I/O* 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O* 16 I/O 17 I/O 18 GND 19 VCC 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O* 29 I/O 30 I/O 31 I/O* 32 I/O* 33 I/O 34 I/O* 35 I/O 36 M1-RD 37 ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PQFP PQFP XC3064, XC3090, Pin Number XC3195 Pin Number * 1 I I I I I I I/O 53 ...
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... XC3000 Families 175-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PGA Pin PGA Pin XC3090, XC3195 Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 C14 B3 I/O B15 C4 I/O D14 B4 I/O C15 A4 I/O E14 D5 I/O B16 C5 I/O D15 B5 I/O C16 A5 I/O D16 C6 I/O F14 D6 I/O E15 ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number XC3090 1 PWRDWN 2 TCLKIN-I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 GND 23 VCC 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 ...
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... XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number Number XC3090 1 – 2 GND 3 PWRDWN 4 TCLKIN-I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 – 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 GND 26 VCC 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 – 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Description PG223 PQ208 A9-I/O B1 206 A10-I/O E3 205 I/O E4 204 I/O C2 203 I/O C1 202 I/O D2 201 A8-I/O E2 200 A11-I/O F4 199 I/O F3 198 I/O D1 197 I/O F2 196 I/O G2 194 A7-I/O G4 193 A12-I/O G1 192 I/O H2 191 I/O H3 190 I/O H1 189 I/O H4 188 I/O J3 187 I/O J2 186 A6-I/O J1 185 A13-I/O K3 184 VCC J4 183 ...
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XC3000 Component Availability PINS TYPE PLAST. PLAST. PLAST. PLAST. PLCC VQFP PLCC PLCC PC44 VQ64 PC68 PC84 CODE XC3020 -50 - -100 -125 C C XC3030 -50 -70 C ...
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... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed lists of package pin-outs, see pages 2-140 through 2-150. ...