xc3100 Xilinx Corp., xc3100 Datasheet - Page 30

• Manufacturer Part Number: xc3100
• Description: Logic Cell Array Families
• Manufacturer: Xilinx Corp.

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
General LCA Switching Characteristics
Notes: 1. At power-up, V
DONE/PROG
RESET (2)
DONE/PROG
PWRDWN (3)
V
M0/M1/M2
PWRDWN
CC
(Output)
RESET
(Valid)
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
3. PWRDWN transitions must occur while V
INIT
layed by holding RESET Low until V
a non-monotonically rising V
D/P after V
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
User State
M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
Width (Low) required for Re-config.
INIT response after D/P is pulled Low 6
Power Down V
cc
has reached 4.0 V (2.5 V for XC3000L).
cc
must rise from 2.0 V to V
2 T
MR
Description
5 T
CC
cc
PGW
6 T
may require a >1- s High level on RESET, followed by a >6- s Low level on RESET and
PGI
cc
has reached 4.0 V (2.5 V for XC3000L). A very long V
3 T
cc
CC
RM
>4.0 V(2.5 V for XC3000L).
Clear State
min in less than 25 ms. If this is not possible, configuration can be de-
2-132
2
3
4
5
Symbol
V
T
T
T
T
T
CCPD
MRW
PGW
PGI
MR
RM
4 T
MRW
Min
2.3
1
3
6
6
Max
Configuration State
cc
7
Note 3
rise time of >100 ms, or
V
CCPD
Units
V
s
s
s
s
s
X5387