xc6vcx75t Xilinx Corp., xc6vcx75t Datasheet - Page 38

• Manufacturer Part Number: xc6vcx75t
• Description: Virtex-6 Cxt Family Data Sheet
• Manufacturer: Xilinx Corp.

Table 50: Block RAM and FIFO Switching Characteristics (Cont’d)
DS153 (v1.4) July 28, 2010
Advance Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. T
11. The FIFO reset must be asserted for at least three positive clock edges.
Maximum Frequency
F
F
F
F
MAX
MAX_CASCADE
MAX_FIFO
MAX_ECC
TRACE will report all of these parameters as T
T
These parameters also apply to synchronous FIFO with DO_REG = 0.
T
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
T
The ADDR setup and hold must be met when EN is asserted
possible.
T
RCKO_DOR
RCKO_DO
RCKO_FLAGS
RCKO_POINTERS
RCKO_DI
RCO_FLAGS
Symbol
includes both A and B inputs as well as the parity inputs of A and B.
includes T
includes T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
includes the following parameters: T
includes both T
RCKO_DOP
RCKO_DOW
as well as the B port equivalent timing parameters.
Block RAM
(Write First and No Change modes)
Block RAM (Read First mode)
Block RAM (SDP mode)
Block RAM Cascade
(Write First and No Change modes)
Block RAM Cascade (Read First mode)
FIFO in all modes
Block RAM and FIFO in ECC configuration
, T
RCKO_RDCOUNT
RCKO_DOPR
RCKO_DO
, and T
and T
RCKO_AEMPTY
RCKO_DOPW
RCKO_WRCOUNT.
.
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Description
(even when WE is deasserted)
, T
RCKO_AFULL
as well as the B port equivalent timing parameters.
, T
RCKO_EMPTY
. Otherwise, block RAM data corruption is
, T
RCKO_FULL
Virtex-6 CXT Family Data Sheet
400
400
400
350
400
400
325
, T
-2
Speed Grade
RCKO_RDERR
350
347
347
347
304
350
282
-1
, T
RCKO_WRERR.
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
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