mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 48

• Manufacturer Part Number: mc68hc05bs8
• Description: Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
• Manufacturer: Freescale Semiconductor, Inc

6
6.1.2
The 16-bit Output Compare register is used for several purposes, such as indicating when a period
of time has elapsed. All bits are readable and writable and are not affected by the timer hardware
or reset. If the compare function is not needed, the Output Compare register can be used as
storage locations.
The contents of the Output Compare register are continually compared with the contents of the
free-running counter and, if a match is found, the output compare flag (OCF) in the Timer Status
register is set. The Output Compare register’ value should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany a successful
output compare provided the interrupt enable bit (OCIE) is set. (The free-running counter is
updated every four internal bus clock cycles.)
After a processor write cycle to the Output Compare register containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare
function. The processor can write to either byte of an Output Compare register without affecting
the other byte. The minimum time required to update the Output Compare register is a function of
the program rather than the internal hardware. Because the output compare flag and Output
Compare register are not defined at power on, and not affected by reset, care must be taken when
initializing output compare functions with software. The following procedure is recommended:
6.1.3
‘Input Capture’ is a technique whereby an external signal (connected to TCAP pin) is used to
trigger a read of the free-running counter. In this way it is possible to relate the timing of an external
signal to the internal counter value, and hence to elapsed time.
6-4
1) write to Output Compare register High-byte to inhibit further compares;
2) read the Timer Status register to initialize clearing of OCF;
3) write to Output Compare register Low-byte to enable the output compare
function.
OCMPH
OCMPL
ICAPH
ICAPL
Output Compare Register
Input Capture Registers
Address bit 7
Address bit 7
$0016
$0017
$0014
$0015
OC15 OC14 OC13 OC12 OC11 OC10
OC7
IC15
IC7
bit 6
OC6
bit 6
IC14
TIMERS
IC6
IC13
bit 5
OC5
bit 5
IC5
bit 4
OC4
bit 4
IC12
IC4
IC11
bit 3
OC3
bit 3
IC3
bit 2
OC2
bit 2
IC10
IC2
bit 1
OC9
OC1
bit 1
IC9
IC1
MC68HC05BS8
bit 0
OC8 unaffected
OC0 unaffected
bit 0
IC8
IC0
unaffected
unaffected
on reset
on reset
State
State
TPG