mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 83

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mc68hc05bs8

Manufacturer Part Number
mc68hc05bs8
Description
Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
Manufacturer
Freescale Semiconductor, Inc
Datasheet
9.9
The circuit is responsible for generating the SAM signal for the Video Chip set. The SAM signal is
a sampling signal, which outputs a positive pulse at the Vsync pulse, and outputs another positive
pulse when the value of the Sampling Pulse register matches the horizontal line counter. The
pulse width is equal to one horizontal line period.
9.10
There are six registers associated with the Sync Signal Processor, these are described below.
9.10.1
VPOL - Vertical Sync Input Polarity
Vertical Sync Input Polarity flag indicates the polarity of the incoming signal at the VSYNC input.
HPOL - Horizontal Sync Input Polarity
Horizontal Sync Input Polarity flag indicates the polarity of the incoming signal at the HSYNC
input.
VDET - Vertical Sync Signal Detect
This bit is set when an active vertical sync signal is detected on the VSYNC pin. If cleared, it
indicates there is no active signal, and the VTTL will output the internally generated Vsync signal.
An active vertical sync signal is defined as:
VDET = (VSYNC pulse width < 1024t
MC68HC05BS8
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Address
$000A
Sampling Pulse Output
SSP Registers
Sync Signal Control and Status Register (SSCSR)
VPOL
bit 7
VSYNC input is positive polarity.
VSYNC input is negative polarity.
HSYNC input is positive polarity.
HSYNC input is negative polarity.
An active vertical sync is detected at VSYNC input.
No vertical sync signal at VSYNC input; use internal generated
Vsync for VTTL.
HPOL
bit 6
VDET
SYNC SIGNAL PROCESSOR
bit 5
CYC
) · (15.36x10
HDET
bit 4
3
SOUT
bit 3
t
CYC
< VSYNC period < 48.128x10
INSRT
bit 2
SIN1
bit 1
SIN0
bit 0
0000 0000
3
on reset
t
State
CYC
)
TPG
9

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