mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 50

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mc68hc05bs8

Manufacturer Part Number
mc68hc05bs8
Description
Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
Manufacturer
Freescale Semiconductor, Inc
Datasheet
6
TOIE - Timer Overflow Interrupt Enable
IEDG - Input Edge
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture registers. When clear, a negative-going edge triggers the
transfer.
OLVL - Output Level Voltage Latch
When OLVL is set high output level will be clocked into the output level register by the next
successful output compare on the TCMP pin.
6.1.5
The Timer Status register contains the status bits for the above three interrupt conditions - ICF,
OCF, and TOF.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF - Input Capture Flag
This bit is set when the selected polarity of edge is detected by the input capture edge detector;
an input capture interrupt will be generated, if ICIE is set, ICF is cleared by reading the TSR and
then the Input Capture Low register ($15)
6-6
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
TSR
Timer Status Register (TSR)
Timer Overflow interrupt enabled.
Timer Overflow interrupt disabled.
TCAP is positive-going edge sensitive.
TCAP is negative-going edge sensitive.
High output on TCMP pin if counter compare is true.
Low output on TCMP pin if counter compare is true.
A valid input capture has occurred.
No input capture has occurred.
Address bit 7
$0013
ICF
bit 6
OCF
TIMERS
bit 5
TOF
bit 4
0
bit 3
0
bit 2
0
bit 1
0
MC68HC05BS8
bit 0
0
uuu0 0000
on reset
State
TPG

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