mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 104

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Local Bus Controller
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by t
The following figure shows how the AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.
1
2
2.15.2.3
All output signal timings are relative to the falling edge of any LCLKs for PLL bypass mode. The external circuit must use the
rising edge of the LCLKs to latch the data.
All input timings except LUPWAIT/LFRB are relative to the rising edge of LCLKs. LUPWAIT/LFRB are relative to the falling
edge of LCLKs.
104
t
t
addr
arcs
, t
is programmable and determined by LCRR[EADC] and ORx[EAD].
LGPL2/LOE_B
awcs
LSYNC_IN
LAD[0:31]
acs
, t
LWE_B
aoe
LBCTL
LCS_B
(0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is t
LALE
Enhanced Local Bus AC Timing Specifications for PLL Bypass Mode
, t
rc
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
, t
oen
, t
awe
address
t
addr
Figure 58. GPCM Output Timing Diagram (PLL Enabled)
, t
wc
, t
wen
t
LBONOT
t
are determined by ORx. Refer to reference manual.
t
aoe
arcs
+ t
+ t
read data
LBKHOV
LBKHOV
read
t
rc
t
t
oen
LBKHOX
address
t
addr
acs
+ t
LBKHOV
t
LBONOT
t
awcs
t
.
awe
+ t
write
t
write data
wc
+ t
LBKHOV
LBKHOV
Freescale Semiconductor
t
wen