mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 76

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

HDLC, BISYNC, Transparent, and Synchronous UART Interfaces
2.8.2
The following table provides the input and output AC timing specifications for the HDLC, BISYNC, and Transparent protocols.
The following table provides the input and output AC timing specifications for the synchronous UART protocols.
76
For recommended operating conditions, see
For recommended operating conditions, see
Outputs—Internal clock delay
Outputs—External clock delay
Outputs—Internal clock high Impedance
Outputs—External clock high Impedance
Inputs—Internal clock input setup time
Inputs—External clock input setup time
Inputs—Internal clock input hold time
Inputs—External clock input hold time
Notes:
1. The symbols used for timing specifications follow the pattern t
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
Outputs—Internal clock delay
Outputs—External clock delay
Outputs—Internal clock high Impedance
Outputs—External clock high Impedance
Inputs—Internal clock input setup time
Inputs—External clock input setup time
Inputs—Internal clock input hold time
Inputs—External clock input hold time
Notes:
1. The symbols used for timing specifications follow the pattern t
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
and t
timing (HI) for the time t
are measured at the pin.
and t
timing (HI) for the time t
are measured at the pin.
(first two letters of functional block)(reference)(state)(signal)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Characteristic
Characteristic
Table 44. HDLC, BISYNC, and Transparent AC Timing Specifications
serial
serial
Table 45. Synchronous UART AC Timing Specifications
memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 3
Table 3
for outputs. For example, t
for outputs. For example, t
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
HEKHOV
HEKHOX
HEKHOV
HEKHOX
t
t
t
t
HIKHOV
HIKHOX
(first two letters of functional block)(signal)(state)(reference)(state)
HIKHOV
HIKHOX
(first two letters of functional block)(signal)(state)(reference)(state)
HEIVKH
HEIXKH
HEIVKH
HEIXKH
HIIVKH
HIIXKH
HIIVKH
HIIXKH
1
1
Min
Min
1.3
10
0
1
0
1
6
4
0
0
1
0
1
8
0
1
HIKHOX
HIKHOX
symbolizes the outputs internal
symbolizes the outputs internal
Max
Max
5.5
8.4
5.5
11
14
11
14
—
—
—
—
—
—
—
—
8
Freescale Semiconductor
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for inputs
for inputs
Notes
Notes
—
—
—
—
—
—
—
—
2
2
2
2
2
2
2
2