mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 117
mpc8569e
Manufacturer Part Number
mpc8569e
Description
Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8569E.pdf
(126 pages)
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The following figure provides the AC test load for the UTOPIA/POS.
Figure 71
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
The following figure shows the UTOPIA/POS timing with external clock.
Freescale Semiconductor
UTOPIA/POS inputs—External clock input setup time
UTOPIA/POS inputs—Internal clock input hold time
UTOPIA/POS inputs—External clock input hold time
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
2. The symbols used for timing specifications follow the pattern t
measured at the pin.
and t
outputs internal timing (UI) for the time t
invalid (X).
(first two letters of functional block)(reference)(state)(signal)(state)
UTOPIACLK (Input)
and
Output Signals:
Figure 72
Input Signals:
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
UTOPIA
UTOPIA
Characteristic
represent the AC timing from
Table 80. UTOPIA/POS AC Timing Specifications
Figure 71. UTOPIA/POS AC Timing (External Clock) Diagram
Output
t
UEIVKH
Figure 70. UTOPIA/POS AC Test Load
Utopia
memory clock reference (K) goes from the high state (H) until outputs (O) are
Z
0
= 50 Ω
Table
for outputs. For example, t
80. Note that although the specifications generally reference the
t
UEKHOV
t
(first two letters of functional block)(signal)(state)(reference)(state)
UEIXKH
Symbol
t
t
t
UEIVKH
UEIXKH
UIIXKH
t
UEKHOX
2
R
L
= 50 Ω
1
(continued)
Min
4.0
1.2
UIKHOX
0
OV
DD
symbolizes the UTOPIA/POS
/2
UTOPIA/POS Interface
Max
—
—
—
for inputs
Unit
ns
ns
ns
117